vendor: 19,616 bytes, lines 1-41
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å°ä½",dateDisplay:"2024å¹´4æ16æ¥"},"movellus-introduces-aeonic-insight-product-line-for-on-die-telemetry":{title:"Movellus æ¨åº Aeonic Insight⢠产åçº¿ï¼æä¾çä¸é¥æµ",dateDisplay:"2023å¹´11æ14æ¥"},"movellus-delivers-clock-generation-module-on-3nm-process":{title:"Movellus å¨ 3nm å·¥èºä¸äº¤ä»æ¶éçææ¨¡åï¼CGMï¼",dateDisplay:"2023å¹´10æ24æ¥"},"movellus-integrated-droop-response-system":{title:"Movellus åå¸ä¸çé¦ä¸ªé¢å SoC çéæå¼çµå骤éååºç³»ç»",dateDisplay:"2023å¹´6æ13æ¥"}},uo="Movellus, the Movellus logo, Aeonic, Aeonic Generate, Aeonic Power, Aeonic Insight, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners.",Qc={"movellus-samsung-safe-pr":{eyebrow:"Press Release",title:"Movellus Brings Power Optimization IP to Samsung Electronicsâ Advanced Nodes",deck:"Equips AI and HPC chip designers with on-die power optimization and advanced telemetry IP to unlock next-generation power efficiency.",location:"Santa Clara, California",dateDisplay:"August 11, 2026",datetime:"2026-08-11",source:"Movellus",lede:"Movellus today announced a collaboration with Samsung Electronics, making its Aeonic® platform for on-die power optimization and telemetry IP available to AI and HPC chip designers through the Samsung Advanced Foundry Ecosystem (SAFEâ¢) Program. Designers can license the IP for Samsung Foundryâs advanced process nodes to manage power and maximize performance for advanced SoC de
49signs.",blocks:[{type:"p",text:"The Aeonic platform gives AI and HPC designers a complete solution for on-die power control loops. It provides high-resolution telemetry and nanosecond actuators that continuously monitor and resolve transient power events. These capabilities let designers run silicon closer to its performance limits on Samsung Foundryâs advanced processes, with the visibility needed to maintain reliable high performance across the system lifecycle."},{type:"quote",text:"âAs power management becomes increasingly critical for AI and HPC designs, Samsung Foundryâs 4nm technology combined with Movellusâ Aeonic platform helps customers build more energy-efficient and power-aware SoCs for todayâs AI, HPC and data center workloads. Together, we are helping designers accelerate deployment while providing greater visibility into silicon operation and performance.â",name:"Ben Rhew",role:"Corporate Vice President and Head of the Foundry IP Development Team, Samsung Electronics"},{type:"quote",text:"âPower is setting the ceiling for scalability in AI and HPC SoC design. The Aeonic® product family provides designers of advanced SoCs with a new level of control and visibility for their designs to optimize power and performance and improve reliability. Our partnership with SAFE now brings Movellus IP solutions to the broader Samsung Foundry customer base.â",name:"Vikram Karvat",role:"Chief Operating Officer, Movellus"}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical power and performance optimization technology integrated into an array of applications, ranging from edge AI devices to performance-centric cloud data center compute and networking offerings. The company is headquartered in Santa Clara, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]},{heading:"Media Contact",paragraphs:["Aakash Jani","[email protected]"]}],fineprint:uo},"synopsys-movellus-partner-pr":{eyebrow:"Press Release",title:"Movellus Partners with Synopsys to Deliver Power Efficiency for Next-Generation ICs",deck:"Movellusâ adaptive clocking technology is now available to Synopsys SLM IP customers.",location:"Santa Clara, California",dateDisplay:"March 10, 2026",datetime:"2026-03-10",source:"GlobeNewswire",lede:"Movellus announced the inclusion of its clocking technology in the Synopsys Silicon Lifecycle Management (SLM) IP portfolio, directly addressing power challenges facing complex chips in the age of AI. The Synopsys SLM Advanced Clock Generator (âACGâ) IP serves as the foundation for real-time power optimization, enabling power architects to dynamically adapt SoC profiles to environmental and workload changes, optimizing performance and power. The OEM relationship expands customer access to Movellusâ adaptive clocking technology through Synopsysâ channels.",blocks:[{type:"quote",text:"âAs AI and hyperscale workloads push the boundaries of semiconductor complexity, managing power optimization and power integrity has become a key challenge for our customers. By integrating Movellusâ innovative technology into our Silicon Lifecycle Management portfolio, we are providing power architects with a sophisticated, real-time solution to optimize power efficiency.â",name:"Steve Pateras",role:"Vice President of SLM Product Management, Synopsys"},{type:"p",text:"The Synopsys SLM ACG IP delivers high-performance, adaptive clock generation for droop mitigation and Dynamic Frequency Scaling (DFS) / Dynamic Voltage and Frequency Scaling (DVFS) applications. The ACG IP provides ultra-fast adaptive clocking, extensive programmability to address varied use cases, and advanced telemetry to monitor droop events, DFS/DVFS transitions, and clock health."},{type:"quote",text:"âThe combination of Synopsysâ sensor portfolio and Movellusâ adaptive clocking IP provides a comprehensive power, thermal, and performance optimization platform to our mutual customers. Weâre very excited about where this will take the industry in the future.â",name:"Vikram Karvat",role:"Chief Operating Officer, Movellus"},{type:"p",text:"Movellus continues to advance high-performance silicon through feature-rich IP. The Aeonic⢠IP platform has been integrated by multiple customers across various process nodes, with applications ranging from performance-centric cloud datacenter compute and AI offerings to ultra-low-power edge AI devices. This milestone broadens access to Movellus technology, which when combined with the Synopsys SLM solutions will attract a wider customer base for advanced SoCs, AI accelerators, and processors. The Synopsys SLM ACG IP will be demonstrated at the Synopsys User Group (SNUG) as part of Synopsys Converge 2026, March 11-12 in Santa Clara, California."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical power and performance optimization technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Santa Clara, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]}],fineprint:uo},"movellus-quicklogic-press-release":{eyebrow:"Press Release",title:"Movellus Advanced Clocking IP Selected for QuickLogicâs Strategic Radiation-Hardened FPGA Program",deck:"Movellus Aeonic Generate⢠IP Family Continues Expansion in Defense and Space Applications",location:"Santa Clara, California",dateDisplay:"March 9, 2026",datetime:"2026-03-09",source:"GlobeNewswire",lede:"Movellus today announced that its high-performance clocking technology has been selected for QuickLogic Corporationâs (NASDAQ: QUIK) Strategic Radiation Hardened (SRH) FPGA program. This partnership marks a significant step forward in securing the domestic supply chain for highly reliable, programmable logic in the worldâs most demanding strategic environments.",blocks:[{type:"quote",text:"âOur partnership with Movellus is a key component in the successful execution of our Strategic Radiation Hardened FPGA program. This integration will support our broader objective of providing the defense and aerospace industries with a robust, domestically sourced and fabricated programmable logic platform that meets the rigorous demands of strategic-grade applications.â",name:"Brian Faith",role:"President and CEO, QuickLogic"},{type:"quote",text:"âCollaborating with QuickLogic underscores the importance of resilient IP for high reliability, mission-critical applications. Through our involvement in this initiative, we are helping to ensure that next-generation defense, aerospace and space systems have the robust clocking foundation necessary to maintain performance and reliability in the most challenging environments.â",name:"Mo Faisal",role:"CEO, Movellus"}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical power and performance optimization technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Santa Clara, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]}],fineprint:uo},"pdn-iq-launch":{eyebrow:"Press Release",title:"Movellus Debuts Industry-First On-Die Power Delivery Network Analyzer",deck:"Aeonic Insight PDN IQ arms industry with unprecedented transistor-level PDN visibility and analytics that spans the entire product cycle from bench to in-field monitoring.",location:"Santa Clara, California",dateDisplay:"May 1, 2025",datetime:"2025-05-01",source:"GlobeNewswire",lede:"Movellus today announced the industryâs first on-chip sensor for power delivery network (PDN) characterization and monitoring. Power integrity is vital to the performance and efficie
49ncy of any system-on-chip (SoC). However, the industry has very limited visibility into the behavior of on-chip PDNs, which can result in voltage over-margining (compromising both power and performance), missed performance targets, and higher DPPM rates. And as the industry evolves to larger SoCs, stacked die, and chiplets, the problem is further magnified, making PDN visibility even more critical to overall system performance and energy efficiency. PDN IQ enables improvements in power, performance, and uptime for advanced semiconductors by providing PDN visibility across the entire silicon lifecycle from bench characterization and production test to in-field monitoring.",blocks:[{type:"quote",text:"âRobust PDN operation is required to ensure the functionality and performance of high end SoCs. Today, the industry relies on a variety of black-box techniques to evaluate these critical networks, but these approaches are becoming less effective in the face of ever larger devices, advanced packaging, and severe power swings in workloads. Having direct visibility of PDN efficacy, anywhere on chip, is a compelling mechanism to optimize the power-performance characteristics of large SoCs and will be a game changer for the industry.â",name:"Ranganathan âSudsâ Sudhakar",role:"Chief Development Officer, d-Matrix"},{type:"quote",text:"âThe insatiable demand for greater bandwidth in AI accelerators continues to expand the quantity of processor and memory chiplets integrated within a single device. As disparate semiconductors are knitted together with advanced packaging technologies, such as Decaâs M-Series fan-out, optimized power delivery is an inherent challenge. The introduction of this exciting new in-situ power delivery network telemetry from Movellus gives customers a breakthrough capability to optimize voltage-frequency points to maximize performance while improving system quality and reliability.â",name:"Tim Olson",role:"CEO, Deca Technologies"},{type:"list",intro:"Aeonic Insight PDN IQ delivers high-speed, transistor-level voltage telemetry combined with sophisticated trigger and trace capabilities, and advanced statistics that deliver value throughout the entire silicon lifecycle. Some of the use cases include:",items:["Refining voltage-frequency curves during characterization","Observing on-die PDN behavior under high-stress workloads on the bench and in field","Improving screening accuracy to reduce DPPM rates in production","Improving fleet uptime by continuously monitoring PDN behavior and flagging anomalies"]},{type:"quote",text:"âSoCs are growing exponentially in complexity, especially for the datacenter and AI segments. Design teams need to turn over every rock in their designs to optimize for power and performance, and this includes the power delivery network. Movellus is arming its customers with the visibility and telemetry required to optimize SoC power with their new on-die PDN analyzer IP.â",name:"Rich Wawrzyniak",role:"Principal Analyst, SHD Group"},{type:"p",text:"Aeonic Insight⢠PDN IQ can also integrate with third-party analytics platforms, offering even greater flexibility. Silicon teams can feed telemetry data from the trace buffer and other registers available in the IP into an analytics stack to gain deeper insights into PDN behavior, further enhancing design and deployment strategies."},{type:"p",text:"Movellus continues to advance high-performance silicon through feature-rich IP. The Aeonic⢠Digital IP platform has been integrated by multiple customers across various process nodes, with applications ranging from performance-centric cloud datacenter compute and AI offerings to ultra-low-power edge AI devices. This latest milestone enables advanced on-die observability for power delivery networks, ensuring maximum power efficiency for cutting-edge SoCs, AI accelerators, and processors."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Santa Clara, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Aeonic Power, Elevating Silicon, Aeonic Insight, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."},"movellus-rtx-seakr-pr":{eyebrow:"Press Release",title:"Movellus and RTXâs SEAKR Engineering Collaborate on Advancing Mission-Critical ASICs",deck:"Movellus Continues Supp
49ort for Secure Microelectronics with Radiation-Tolerant Ready, Observable, Digital IP",location:"Santa Clara, California",dateDisplay:"April 1, 2025",datetime:"2025-04-01",source:"GlobeNewswire",lede:"Movellus announced today that RTXâs SEAKR Engineering, LLC, selected the Aeonic⢠Generate Intellectual Property (IP) Platform for its next-generation radiation-tolerant ASIC designs.",blocks:[{type:"p",text:"As part of the collaboration, Movellus provides a portion of the computer chip designs utilized in SEAKRâs spacecraft payload electronics to maximize ease of integration. Through the observable technology, mission operations staff can easily monitor the health of RTXâs SEAKR ASIC."},{type:"quote",text:"âThe Movellus IP enabled us to quickly meet our block-to-block communication performance goals and mitigate aging effects. With the Movellus team, we have a solution that is robust and tolerant of radiation effects improving the performance and on-orbit availability of our next-generation ASICs.â",name:"Steve Tigner",role:"Director of ASIC Development, SEAKR Engineering"},{type:"p",text:"The next generation of military and aerospace designs requires sophisticated computing capabilities built on advanced process technology. Movellusâ high-performance, synthesizable IP helps partners deliver on these requirements. The Aeonic⢠Digital IP portfolio enables easy migration across advanced process nodes with a radiation-tolerant ready architecture that also provides mission-mode telemetry information."},{type:"p",text:"Movellus continues to advance high-performance silicon through feature-rich, synthesizable IP, with a unique, radiation-hardened ready architecture that enables increased use of commercial technology in military and aerospace applications. This is a pillar of U.S. Government technology strategy in areas including the Department of Defense Microelectronic Activity initiative. The Aeonic⢠Digital IP portfolio, implemented across various process nodes from 40nm to 3nm, complements this charter."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Santa Clara, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]},{heading:"About SEAKR Engineering",paragraphs:["SEAKR Engineering, LLC, is RTXâs leading-edge provider of advanced payload and mission solutions for space applications. For more than 40 years, we have developed and delivered reliable and innovative solutions across a wide range of space systems. SEAKR is headquartered in Centennial, Colorado."]},{heading:"About RTX",paragraphs:["With more than 185,000 global employees, RTX pushes the limits of technology and science to redefine how we connect and protect our world. Through industry-leading businesses â Collins Aerospace, Pratt & Whitney, and Raytheon â we are advancing aviation, engineering integrated defense systems, and developing next-generation technology solutions and manufacturing to help global customers address their most critical challenges. The company, with 2023 sales of $69 billion, is headquartered in Arlington, Virginia."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Elevating Silicon, Aeonic Insight, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits, Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."},"tenstorrent-and-movellus-form-strategic-engagement-for-next-generation-chiplet-based-ai-and-hpc-solutions":{eyebrow:"Press Release",title:"Tenstorrent and Movellus Form Strategic Engagement for Next-Generation Chiplet-Based AI and HPC Solutions",deck:"Enabling Cross-Foundry IP for Power and Performance Optimization",location:"Sunnyvale, California",dateDisplay:"September 9, 2024",datetime:"2024-09-09",source:"GlobeNewswire",lede:"Movellus and Tenstorrent announced that Tenstorrent has licensed Movellusâ digital IP family as part of a strategic engagement for its AI and HPC chiplet solutions. This collaboration aims to leverage the strengths of both companies to develop chiplet-based solutions that enhance performance while optimizing power consumption. Movellus Aeonic Digital IP allows Tenstorrent to leverage advanced clocking techniques to reduce overall energy consumption.",blocks:[{type:"quote",text:"âBy collaborating with Movellus and integrating their technology, we are optimizing power efficiency in our processors and continuing to drive Tenstorrentâs leadership in scalable AI chiplets.â",name:"Keith Witek",role:"Chief Operating Officer, Tenstorrent"},{type:"p",text:"Movellusâ Aeonic portfolio offers products designed to tackle critical infrastru
49cture challenges in modern computing, such as on-die sensing, digital clocking, and power delivery. Notably, the digital adaptive clocking family facilitates architectural advancements like per-core distributed clocking and fine-grained dynamic frequency scaling (DFS). Additionally, when coupled with droop detectors, these products provide advanced clock management capabilities, allowing for Vmin reduction by effectively mitigating droop while minimizing any performance impact. With these products it is possible to combine localized clocking, DFS, DVFS, and droop mitigation in a unified solution, simplifying design and easing integration."},{type:"quote",text:"âMovellusâ digital clocking technology enables us to distribute digital PLLs across our chip to provide a localized, fine-grained clocking, something that is not possible with traditional analog PLLs. In addition, their process agnostic digital architecture provides a cohesive software interface across multiple devices.â",name:"Michael Smith",role:"Senior Director of SoC Hardware Engineering, Tenstorrent"},{type:"quote",text:"âTenstorrent is pioneering AI and HPC compute with their novel and scalable hardware architectures and software stack. We are grateful to be a part of this ground-up approach that is foundational to the advancement of AI and HPC compute with an intention of maximizing energy efficiency â a much-needed development in the age of AI.â",name:"Mo Faisal",role:"CEO, Movellus"},{type:"p",text:"To learn more about Movellus, meet us at the upcoming AI Hardware and Edge AI Summit. Movellus will showcase its award-winning IP portfolio for energy optimization at Booth 68."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Sunnyvale, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]},{heading:"About Tenstorrent",paragraphs:["Tenstorrent is a next-generation computing company that builds computers for AI. Headquartered in Toronto, Canada, with U.S. offices in Austin, Texas, and Silicon Valley, and global offices in Belgrade, Tokyo, Bangalore, Singapore, and Seoul, Tenstorrent brings together experts in the field of computer architecture, ASIC design, advanced systems, and neural network compilers. Tenstorrent is backed by Eclipse Ventures and Real Ventures, among others. Learn more at tenstorrent.com."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Aeonic Power, Elevating Silicon, Aeonic Insight, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."},"silicon-catalyst-ikp":{eyebrow:"Press Release",title:"Movellus Joins the Silicon Catalyst In-Kind Partner Ecosystem",deck:"Both companies are exhibiting at the upcoming AI Summit",location:"Silicon Valley, California",dateDisplay:"August 13, 2024",datetime:"2024-08-13",source:"GlobeNewswire",lede:"Movellus today announced that it has joined the Silicon Catalyst ecosystem as the newest member of their In-Kind Partner (IKP) network. Silicon Catalyst is the only incubator + accelerator focused on the global semiconductor industry including Chips, Chiplets, Materials, IP and Silicon fabrication-based Photonics, MEMS, Sensors, Life Science and Quantum. The Silicon Catalyst IKPs provide technical and business support to the Portfolio Companies in the incubator + accelerator, enabling them to tap into the products and services available to enhance the growth of their companies.",blocks:[{type:"p",text:"Silicon Catalyst Portfolio Companies will now have access to the Movellus high-performance energy and performance-optimized infrastructure IP for their complex SoCs. The Movellus Aeonic⢠Digital IP platform comprises product families targeted at: on-die sensing to provide visibility required to solve significant challenges like SDC (Silent Data Corruption), digital clocking which allows for architectural innovation through novel strategies like per-core distributed clocking or fine-grained DVFS (Digital Voltage and Frequency Scaling), and on-die power delivery to maximize energy s
49avings through per-core DVFS. End applications range from ultra-low-power edge AI devices to performance-centric cloud datacenter compute and AI offerings."},{type:"quote",text:"âMovellus is excited to be working with the incredible community of start-ups that Silicon Catalyst has enabled. The inevitable migration from yesterdayâs analog clocking approaches to the smaller, distributed, observable digital clocking architectures that feed silicon lifecycle analytics platforms is happening now. It is the forward-thinking companies in the Silicon Catalyst portfolio that are leading the charge for innovative architectures required to develop modern AI chips and other leading-edge SoCs.â",name:"Lee Vick",role:"Vice President of Strategic Marketing, Movellus"},{type:"quote",text:"âAdding Movellus as our latest IKP extends our ability to provide the most advanced IP available to our start-ups. The billions of transistors required to develop industry leading solutions will necessitate modular digital designs, and Movellus is the undisputed leader in digital clocking technologies. This collaboration with Movellus will help tool the next generation of silicon startups with observable and energy-optimized infrastructure IP.â",name:"Pete Rodriguez",role:"CEO, Silicon Catalyst"},{type:"p",text:"Silicon Catalyst has developed an unparalleled support ecosystem for its semiconductor start-ups, providing a strong network of financiers, business advisors, and industry professionals who help companies to launch and scale in the market. In addition, the incubator provides privileged access to services, expertise, and intellectual property from the comprehensive network of In-Kind Partners that can empower their companiesâ technological innovation and business growth."},{type:"p",text:"To learn more about Movellus and Silicon Catalyst, meet us at the upcoming AI Hardware and Edge AI Summit. Movellus will be showcasing its award-winning IP portfolio for energy optimization at Booth 68. Silicon Catalyst will be exhibiting in the AI Innovation Village, with personnel from the incubator and the Silicon Catalyst Ventures team to meet with attendees. The show floor will be open from September 10th to 12th at the Signia by Hilton in San Jose, California."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical infrastructure IP for complex SoCs in the AI era. Movellus IP is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Sunnyvale, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]},{heading:"About Silicon Catalyst",paragraphs:["Silicon Catalyst is the worldâs only incubator focused exclusively on accelerating semiconductor solutions, built on a comprehensive coalition of in-kind and strategic partners to dramatically reduce the cost and complexity of development. More than 1200 startup companies worldwide have engaged with Silicon Catalyst, and the company has admitted over 100 exciting companies. Silicon Catalyst supplies startups with access to design tools, silicon devices, networking, and a path to funding, banking and marketing acumen to successfully launch and grow their companiesâ novel technology solutions."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Aeonic Power, Elevating Silicon, Aeonic Insight, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."},"movellus-introduces-aeonic-power-product-family-for-on-die-voltage-regulation":{eyebrow:"Press Release",title:"Movellus Introduces Aeonic Power⢠Product Family for On-Die Voltage Regulation",deck:"First Products Built for High-Current Computational Cores and Die-to-Die Interconnects",location:"Sunnyvale, California",dateDisplay:"June 18, 2024",datetime:"2024-06-18",source:"GlobeNewswire",lede:"Movellus today announced the introduction of the Aeonic Power⢠product family aimed at meeting the on-die power delivery needs of computational blocks, functional blocks, and die-to-die interconnects for complex S
49oCs. The Aeonic Power family debuts with two products: Aeonic Power⢠HC, enabling energy optimization of digital cores and logic blocks, and Aeonic Power⢠LN to simplify power delivery for die-to-die interfaces (e.g. UCIe).",blocks:[{type:"p",text:"Aeonic Power⢠HC is a high-current, on-die solution that delivers local, distributed power, enabling fine-grained DVFS for computational cores, clusters, and logic blocks. It can reliably supply core power to processing elements across a wide current range, helping SoCs balance performance and power, resulting in energy savings of up to 15%."},{type:"quote",text:"âEven with architectural innovations that are improving performance per watt, AI and HPC workloads are driving dramatic increases in total SoC power. The industry is applying every available option to optimize power, and we believe that on-die voltage regulation will be invaluable in helping design teams take the next steps in energy-efficient computing by bringing fine-grained power management closer to computational cores.â",name:"Michael Smith",role:"Senior Director SoC, Tenstorrent"},{type:"p",text:"Aeonic Power⢠LN is built to support die-to-die interconnects in the chiplet ecosystem. Simplifying power distribution for D2D interconnects via on-chip regulation and reduction of inductive filters results in overall BOM improvements for chiplets."},{type:"quote",text:"âPower is a critical design parameter for large SoC design teams. While everyone wants more compute power, it comes at a significant cost at the chip, system and data center levels. Movellus has a very interesting solution to the power challenge with their on-die voltage regulators that enable power management at a silicon block level, closer to each core. Design teams need every advantage to combat growing power demands, and Movellus offers a very valuable solution.â",name:"Kevin Krewell",role:"Principal Analyst, TIRIAS Research"},{type:"p",text:"The Movellus Aeonic Power family delivers a suite of power-focused telemetry, providing valuable insight into customersâ power delivery networks. These features assist engineering teams with a data-driven approach to designing power networks and applying optimal silicon life cycle strategies."},{type:"quote",text:"âPower delivery is one of the most challenging areas in SOC design today. On-die voltage regulation holds tremendous potential to reduce power, simplify design, and increase the robustness of PDNs, but to date, only a handful of companies had the capability to tackle this using custom designs. Aeonic Power takes a new, scalable approach to on-die voltage regulation to make these solutions available to the broader market.â",name:"Mo Faisal",role:"CEO, Movellus"},{type:"list",intro:"Key benefits of Aeonic Power:",items:["Scalable, modular architecture to meet various load requirements","Fine-grain power management for energy optimization","Static IR compensation","Virtual power islands","BOM optimization","Advanced power telemetry","Process portable"]},{type:"p",text:"The Aeonic Power⢠HC and Aeonic Power⢠LN are sampling and will be generally available in 3Q24. For more information on the Aeonic Power⢠product family, visit movellus.com or visit us at DAC in San Francisco, California (Booth #2311) June 24-27, 2024, and join us for an industry panel discussing power management of kW ICs in the DAC main pavilion (2:00 PM PST, Tuesday, June 25, 2024)."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Sunnyvale, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Aeonic Power, Elevating Silicon, Aeonic Insight, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."},"movellus-extends-droop-management-leadership-with-aeonic-generate-awm3":{eyebrow:"Press Release",title:"Movellus Extends Droop Management Leadership with Aeonic Generate⢠AWM3",deck:"Reduces Droop Response Time by up to 50% over Previous Generation while Enhancing Observability",location:"Sunnyvale, California",dateDisplay:"April 16, 2024",datetime:"2024-04-16",source:"GlobeNewswire",lede:"Movellus today announced the exp
49ansion of its award-winning droop response solutions with the Aeonic Generate⢠AWM3. This pioneering solution responds to voltage droops within 1-2 clock cycles while providing enhanced observability for droop profiling. The AWM3 also enables fine-grained dynamic frequency scaling (DFS/DVFS). In combination, the AWM3 droop mitigation and dynamic frequency scaling capabilities reduce the power consumption of complex integrated circuits (ICs) while maintaining the deviceâs operational integrity.",blocks:[{type:"quote",text:"âNowadays, with the ever increasing need of more performance with tighter constraints on power, the importance of DVFS is paramount. Manipulating the clock and the voltage has risks, and the peace of mind given by a smart PLL like the Movellus AWM3 that allows smooth clock transitions and protection against voltage droop is essential to reach the limits of performance.â",name:"Miquel Izquierdo Ustrell",role:"Chief Architect, Semidynamics"},{type:"p",text:"The AWM3 halves the droop response time over the industry leading AWM2 generation and features an unprecedented level of programmability in response profile to meet customersâ individual architectural and dynamic workload requirements. In combination with the Aeonic Insight⢠Droop Detector, the AWM3 provides the industryâs only complete droop detection and response system that also provides insight into droop profiles and clock metrics that can be leveraged by silicon analytics platforms."},{type:"quote",text:"âActive droop management is just what these customers need to manage dynamic voltage droop excursions in-situ and minimize risk of escapes.â",name:"Joseph C. Davis",role:"Senior Director, Calibre Interfaces & mPower Product Management, Siemens Digital Industries Software"},{type:"list",intro:"Key features of the Aeonic Generate AWM3 include:",items:["Extremely fast time to adapt (detect + respond) for droop with fine-grained clock speed control","Rapid response time for DFS/DVFS control","Comprehensive droop and clock health telemetry","Programmable droop response and recovery profile","Support for remote and local droop detection","Standard interfaces for silicon lifecycle management during test and mission mode"]},{type:"p",text:"Movellus continues to advance high-performance silicon through feature-rich, synthesizable IP. The Aeonic⢠Digital IP platform has been integrated by multiple customers across various process nodes, from 40nm to 3nm. End applications range from ultra-low-power edge AI devices to performance-centric cloud datacenter compute and AI offerings. This latest milestone enables advanced on-die observability and droop response to cutting-edge SoCs, AI accelerators, and processors."},{type:"p",text:"The Aeonic Generate⢠AWM3 is available now. For more information on Aeonic Generate AWM3, visit movellus.com/product-overview/aeonic-generate/."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Sunnyvale, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Elevating Silicon, Aeonic Insight, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits, Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."},"movellus-introduces-aeonic-insight-product-line-for-on-die-telemetry":{eyebrow:"Press Release",title:"Movellus Introduces Aeonic Insight⢠Product Line for On-Die Telemetry",location:"Sunnyvale, California",dateDisplay:"November 14, 2023",datetime:"2023-11-14",source:"GlobeNewswire",lede:"Movellus today announced the introduction of the Aeonic Insight product family aimed at meeting the rapidly evolving needs for on-die observability in complex SoCs. The Aeonic Insight product family delivers industry-leading synthesizable sensors that provide actionable silicon insights. These sensors are area-efficient and process-portable, generating advanced telemetry for SoC management and silicon lifecycle analytics platforms.",blocks:[{type:"p",text:"The first product in this family is the Aeonic Insight⢠Droop Detector. This innovative solution enables fine-grained droop detection with multiple thresholds and is amongst the fastest in detection time. The Aeonic Insight observability philosophy also extends to the Aeonic Generate⢠CGM, which introduces detailed clock health telemetry to our industry-leading synthesizable clock generation portfolio."},{type:"quote",text:"âThe rise of large SoCs introduces new silicon design challenges around balancing performance, power and yield, and optimizing sil
49icon health over its lifecycle. Movellus is able to generate advanced on-die telemetry to aid our customers and partners in delivering products with the highest quality, performance, and longevity for advanced applications.â",name:"Vikram Karvat",role:"SVP Products, Marketing, and Planning, Movellus"},{type:"p",text:"Movellus continues to advance high-performance silicon through feature-rich, synthesizable IP. The Aeonic⢠Digital IP platform has been integrated by multiple customers across various process nodes, from 40nm to 3nm. End applications range from ultra-low-power edge AI devices to performance-centric cloud datacenter compute and AI offerings. This latest milestone enables advanced on-die observability to cutting-edge SoCs, AI accelerators, and processors."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Sunnyvale, CA, with R&D centers in Michigan and Toronto. Visit us at movellus.com."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Elevating Silicon, Aeonic Insight, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits, Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."},"movellus-delivers-clock-generation-module-on-3nm-process":{eyebrow:"Press Release",title:"Movellus Delivers Clock Generation Module on 3nm Process",location:"Sunnyvale, California",dateDisplay:"October 24, 2023",datetime:"2023-10-24",source:"GlobeNewswire",lede:"Movellus today announced the availability of Aeonic Generate⢠Clock Generation Module (CGM) on 3nm process. This is the latest in an expanding portfolio of Aeonic Generate products in advanced process nodes. Aeonic Generate CGMs support multi-GHz applications while operating on core voltage supply and are also available as synthesizable.",blocks:[{type:"quote",text:"âTwo key advantages of the Aeonic technology platform is that itâs synthesizable and continues to scale with process. This latest release of our CGM product family continues to demonstrate the efficiency with which we can move products from node to node and leverage the continued scaling factor, leading to improved power and area efficiencies for customers.â",name:"Mo Faisal",role:"CEO, Movellus"},{type:"p",text:"Movellus continues to execute on its mission to enable the next generation of high-performance silicon through its Aeonic⢠Digital IP platform that delivers chip-level architectural innovations to improve system performance through feature-rich, synthesizable IP. Multiple customers have integrated Aeonic Digital IP into their products across process nodes ranging from 40nm to 3nm. End applications span ultra-low-power edge AI devices to performance-centric cloud datacenter compute and AI offerings. This latest milestone enables programmable and synthesizable clock generation for the next era of high-performance SoCs, AI accelerators, and processors."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The company is headquartered in Sunnyvale, CA, with R&D centers in Michigan and Toronto."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Elevating Silicon, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits, Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."},"movellus-integrated-droop-response-system":{eyebrow:"Press Release",title:"Movellus Announces Industry-First Integrated Droop Response System for SoCs",deck:"Aeonic Generate⢠AWM2 Advances Silicon Health and Life Cycle Analytics Ability for ICs",location:"Sunnyvale, California",dateDisplay:"June 13, 2023",datetime:"2023-06-13",source:"GlobeNewswire",lede:"Movellus today announced an industry-first integrated droop response system. This innovative solution is designed to simultaneously address the challenges of voltage droop and enable fine-grained DVFS capability, which in combination can significantly reduce the power consumption of complex integrated circuits while increasing operational reliability. In addition to detecting and responding to voltage droops, the solution incorporates extensive monitoring and observability features that will provide valuable insight to modern silicon health and lifecycle management systems.",blocks:[{type:"p",text:"The AWM2 system adaptation time is amongst the fastest in the industry â similar in performance to full custom solutions but offered as off-the-shelf synthesizable IP. This can result in power saving of more than 10%, making it ideal for complex, power-sensitive SoCs."},{type:"quote",text:"âThe true power of our digital IP platform is demonstrated in our new droop response system. We added autonomous, programmable behavior to our adaptive clocking solution, inserted observability functionality for silicon health and analytics, and developed a cohesive droop response solution that can be delivered as off the shelf IP.â",name:"Mo Faisal",role:"CEO, Movellus"},{type:"p",text:"The integrated droop response system combines droop detection and compensation into a complete integrated system, reducing effort while still gaining maximum benefit. The systemâs observability also provides design engineers greater visibility into S
49oC performance, enabling them to make informed decisions and apply optimal silicon life cycle management strategies."},{type:"quote",text:"âIn todayâs fiercely competitive IC markets, improvements in power efficiency and performance can be a difference-maker. Movellusâ Droop Response System squeezes improvements from the voltage and frequency guardbands that we typically take for granted. Finding these hidden savings and making them easy to deploy is why Movellus is such a great partner to work with.â",name:"Dave Fick",role:"Co-founder and CEO, Mythic"},{type:"quote",text:"âIn the age of many high-performance processors on an SOC, the old rules of thumb about activity factors no longer apply. Even if you have TDP headroom, regulators and on-chip power delivery may not be able to keep up with 1000+ processors all going from idle to full-blast computation. Hardware designers need tools and solutions to solve transient supply droop. The traditional solution is to over-design, operate at a higher voltage, and even lower performance to protect against catastrophic circuit failures. With better tools to identify and better solutions to mitigate transient supply droop, we can operate with higher performance and lower power.â",name:"Darren Jones",role:"Vice President of VLSI Engineering, Esperanto Technologies"},{type:"list",intro:"Key features of the integrated droop response system IP include:",items:["Extremely fast time to adapt (detect + respond) for droop with fine-grained clock speed selection","Extremely fast response time for DVFS control","Industry-first observable droop response system for silicon health and analytics management","Multi-threshold droop detection","Support for remote and local droop detection","APB and JTAG interfaces for silicon health and analytics management during bringup, at production test, and during in-field operation"]},{type:"p",text:"The Aeonic Generate⢠AWM2 is now sampling to select customers. More information on the AWM2 system can be found on the product page or by visiting us at DAC in San Francisco, California (Booth #2417) July 9-13th 2023."}],boilerplate:[{heading:"About Movellus",paragraphs:["Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The team is headquartered in Sunnyvale with R&D centers in Michigan and Toronto. Visit us at movellus.com."]}],fineprint:"Movellus, the Movellus logo, Aeonic, Aeonic Generate, Elevating Silicon, and Intelligent Clock Networks are among the trademarks of Movellus. The term âMovellusâ refers to Movellus Circuits, Inc. and/or its subsidiaries. Other trademarks are the property of their respective owners."}},Ut=[{t:0,max:825,min:785},{t:.5,max:825,min:785},{t:1,max:825,min:785},{t:1.5,max:825,min:785},{t:2,max:825,min:785},{t:2.5,max:825,min:785},{t:3,max:825,min:785},{t:3.5,max:825,min:785},{t:4,max:825,min:785},{t:4.5,max:825,min:785},{t:5,max:825,min:775},{t:5.5,max:825,min:775},{t:6,max:825,min:775},{t:6.5,max:825,min:770},{t:7,max:825,min:765},{t:7.5,max:830,min:760},{t:8,max:830,min:755},{t:8.5,max:835,min:755},{t:9,max:835,min:755},{t:9.5,max:840,min:755},{t:10,max:845,min:750},{t:10.5,max:850,min:750},{t:11,max:850,min:750},{t:11.5,max:860,min:720},{t:12,max:865,min:715},{t:12.5,max:865,min:715},{t:13,max:865,min:715},{t:13.5,max:865,min:715},{t:14,max:865,min:715},{t:14.5,max:865,min:715},{t:15,max:865,min:715},{t:15.5,max:865,min:715},{t:16,max:865,min:715},{t:16.5,max:865,min:715},{t:17,max:865,min:715},{t:17.5,max:865,min:715},{t:18,max:865,min:715},{t:18.5,max:865,min:715},{t:19,max:865,min:715}],Vc=800,Xc=520,xe={top:56,right:40,bottom:56,left:64},Fa=Vc-xe.left-xe.right,ql=Xc-xe.top-xe.bottom,Lc=690,ym=920,Zc=Ut[0].t,bm=Ut[Ut.length-1].t,Gt=h=>xe.left+(h-Zc)/(bm-Zc)*Fa,We=h=>xe.top+(1-(h-Lc)/(ym-Lc))*ql,co=h=>h.map((C,E)=>`${E===0?"M":"L"}${Gt(C.t).toFixed(2)},${We(C.v).toFixed(2)}`).join(" "),xm=180,Sm=({mode:h="hero"})=>{const C=h!=="backdrop",[E,d]=Je.useState(C?0:Ut.length);Je.useEffect(()=>{if(!C)return;if(typeof window!="undefined"&&window.matchMedia&&window.matchMedia("(prefers-reduced-motion: reduce)").matches){d(Ut.length);return}const ue=setInterval(()=>d(Se=>Se>=Ut.length?0:Se+1),xm);return()=>clearInterval(ue)},[C]);const N=C?Ut.slice(0,E):Ut,H=Je.useMemo(()=>N.map(j=>({t:j.t,v:j.max})),[N]),B=Je.useMemo(()=>N.map(j=>({t:j.t,v:j.min})),[N]),F=Je.useMemo(()=>{let j=Ut[0].max;for(const ue of N)ue.max>j&&(j=ue.max);return j},[N]),T=Je.useMemo(()=>{let j=Ut[0].min;for(const ue of N)ue.min<j&&(j=ue.min);return j},[N]),S=C?N[N.length-1]:void 0,V=[700,750,800,850,900],O=[0,4,8,12,16],Q=v.jsxs("svg",{viewBox:`0 0 ${Vc} ${Xc}`,className:"absolute inset-0 h-full w-full",preserveAspectRatio:h==="hero"?"xMidYMid meet":"xMidYMid slice","aria-hidden":!0,
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Line numbers count LF bytes from the start of the resource, as the search results do. Vendor segments are library code the classifier recognised; they are stored but not indexed. Bytes are shown as Latin1 characters, one per byte.