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21 22 23<br><br> 24 25<h1>The HercuLeS high-level synthesis tool</h1> 26 27<table border="0" cellpadding="10" cellspacing="0"> 28 29 <tr> 30 31 <td width="99%" valign="top"> 32 33 <table> 34 35 <tr> 36 37 <td width="67%" align="center"> 38 </td> 39 40 <td width="31%" align="center"> 41<!-- 42 <object data="herc4.svg" width="225" height="300" 43type="image/svg+xml" 44codebase="http://www.adobe.com/svg/viewer/install/" /> 45--> 46 <img src="./hercules_logo.png" align="middle" height="273" border="0"> 47 </td> 48 49 <td width="14%" align="center"> 50 </td> 51 52 </tr> 53 54 </table> 55 56 <br><br> 57 58<a href="https://twitter.com/nkkav" class="twitter-follow-button" data-show-count="true" data-size="small">Follow @nkkav</a>
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70 71</font> 72 73<a href="http://www.reddit.com/submit" onclick="window.location = 'http://www.reddit.com/submit?url=' + encodeURIComponent(window.location); return false"> 74<img src="http://www.reddit.com/static/spreddit7.gif" alt="submit to reddit" border="0"/></a> 75 76 <font class="small_text"> 77 78 <ul> 79 <li><a href="../index.html">Back to main index</a></li><br><br> 80<!-- 81 <li><a href="../cgi-bin/herc.cgi"><b>[NEW] The HercuLeS web interface!!!</b></a></li> 82--> 83 <li><a href="#intro">Introduction</a></li> 84 <li><a href="#overview">Overview</a></li> 85 <li><a href="#howitworks">How it works</a></li> 86 <li><a href="#nac">The NAC programming language</a></li> 87 <li><a href="#gimple2nac">gimple2nac: A prototype C frontend based on GCC GIMPLE</a></li> 88 <li><a href="#nacexamples">Complete examples for the NAC to VHDL flow</a></li> 89 <li><a href="#ansicexamples">Complete examples for the ANSI C to VHDL flow</a></li> 90 <li><a href="#downloads">Other downloads</a></li> 91<!-- 92 <li><a href="#undisclosed">Undisclosed information</a></li> 93--> 94 </ul> 95 96 </font> 97 98 <br><hr size="1"><br> 99 100 <ul> 101 102 <a name="intro"> 103 104 <font class="plain_text">Introduction</font> 105 106 </ul> 107 108 <ol> 109 110 <font class="small_text"> 111 112 <p> 113 HercuLeS is a <a href="http://en.wikipedia.org/wiki/High-level_synthesis">high-level synthesis</a> tool that 114 automatically generates RTL VHDL for non-programmable hardware. HercuLeS translates 115 programs in NAC (a bit-accurate typed-assembly language) to extended FSMDs 116 (Finite-State Machines with Datapath) in VHDL. HercuLeS can also be used for direct 117 synthesis of ANSI C code to VHDL with the help of a prototype <a href="#gimple2nac">translator</a> from 118 <a href="http://gcc.gnu.org/wiki/GIMPLE">GIMPLE</a> (<a href="http://gcc.gnu.org">GCC's</a>) 119 new intermediate representation to NAC. 120 </p> 121 122 <p> 123 Internally, HercuLeS comprises of two main components: a frontend (nac2cdfg) and a graph-based 124 backend (cdfg2hdl): 125 <ul type="disc"> 126 <li><b>nac2cdfg:</b> translator from NAC (N-Address Code) IR, to flat CDFGs represented in <a href="http://www.graphviz.org">Graphviz</a></li> 127 <li><b>cdfg2hdl:</b> the actual HLS tool for automatic FSMD hardware and self-checking testbench generation from Graphviz files to VHDL</li><br> 128 </ul> 129 </p> 130 131 <p> 132 HercuLeS also has an additional ANSI C backend, allowing comparison of NAC programs to 133 reference ANSI C application code and the rapid prototyping of applications (VHDL 134 simulation can be slow depending on design complexity, input data and the simulator used). 135 </p> 136 137 <p> 138 VHDL code generated by HercuLeS can be simulated with <a href="http://ghdl.free.fr">GHDL</a> 139 and the industry-standard <a href="http://www.mentor.com">Modelsim</a>. It is 140 possible to generate VHDL using either the Synopsys packages (the "old" de-facto standard) 141 or the official IEEE library packages. 142 </p> 143 144 <p> 145 HercuLeS supports IEEE-754 floating-point arithmetic 146 (32-bit single and 64-bit double precisions) using the 147 <a href="http://www.eda.org/fphdl/Float_ug.pdf">VHDL-2008 floating-point arithmetic package</a>. 148 </p> 149 150 <p> 151 Further, HercuLeS supports fixed-point arithmetic via 152 sfixed and ufixed vectors as defined by the great <a href="http://www.eda.org/fphdl/">VHDL-2008 fixed-point arithmetic packages</a>
153 by David Bishop. For this option, HercuLeS should be notified (via command-line option) to use the IEEE packages. 154 </p> 155 156 <p> 157 A recent presentation of HercuLeS can be found <a href="./hlstool_pres.pdf">here <b>(UPDATED: 2012-12-21)</b></a>. It is 158 also mentioned in the <a href="#downloads">Downloads</a> section. 159 </p> 160 161 </font> 162 163 </ol> 164 165 <br> 166 167 <br><hr size="1"><br> 168 169 <ul> 170 171 <a name="overview"> 172 173 <font class="plain_text">Overview</font> 174 175 </ul> 176 177 <ol> 178 179 <font class="small_text"> 180 181 <p> 182 The current features of HercuLeS include: 183 <ul> 184 <li>Multiple subprograms (procedures) and procedure calls</li> 185 <li>GIMPLE-to-NAC prototype frontend</li> 186 <li>NAC (N-address code) parsing and semantic analysis</li> 187 <li>Support for SSA form IR (in-to-SSA and out-of-SSA translations) based on Appel's "really-crude" 188 method and Aycock-Horspool's iteratively eliminating algorithms for minimal SSA</li> 189 <li>Translation of NAC input programs to Graphviz CDFGs</li> 190 <li>CDFG (organized as Graphviz graphs) parsing and semantic analysis</li> 191 <li>Support of:</li> 192 <ul> 193 <li>IEEE-754 compliant floating-point arithmetic</li> 194 <li>multi-precision integer (std_logic_vector) and fixed-point (sfixed, ufixed) arithmetic</li> 195 <li>basic low-level IR operators</li> 196 <li>extended FSMD model of computation</li> 197 <li>"scalar" and "streamed" (emitting a series of result values over time) outputs</li> 198 <li>single-dimensional arrays (Multidimensional arrays can always be reduced to 199 single-dimensional ones via matrix flattening)</li> 200 <li>parameter passing through array procedure arguments</li> 201 <li>automatic inference of block-RAM storage (for FPGAs)</li> 202 </ul> 203 <li>Scheduling engines</li> 204 <ul> 205 <li>Sequential scheduling</li> 206 <li>Control-aware ASAP scheduling</li> 207 <li>Control-aware ASAP scheduling with operation chaining (2x-4x better performance)</li> 208 </ul> 209 <li>Optimizations</li> 210 <ul> 211 <li>Register optimization using 212 <a href="http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.27.2462">linear-scan register allocation</a></li> 213 <li>Source-to-source C code optimizer</li> 214 <li>Integration of constant multiplication and <a href="http://sourceforge.net/projects/kdiv">division</a> optimizations</li> 215 <li>Polynomial expression optimizer (WIP)</li> 216 <li>Integration of peephole-based optimizer</li> 217 </ul> 218 <li>Data flow analysis (conservative custom method using on-demand graph reachability checks)</li> 219 <li>Interface to a graph matching (graph and subgraph isomorphism) engine</li> 220 <li>Various APIs:</li> 221 <ul> 222 <li>Common abstract data types</li> 223 <li>Combinatorial objects generator</li> 224 <li>Interval arithmetic</li> 225 <li>Data flow analysis</li> 226 <li>Simple graphs (undirected and directed)</li> 227 <li>Attributed graphs (undirected and directed)</li> 228 </ul> 229 <li>Generators</li> 230 <ul> 231 <li>VHDL design code (FSMD datapath and control)</li> 232 <li>Self-checking VHDL testbench</li> 233 <li>Various script files (Makefiles, shell scripts) for GHDL/Modelsim simulations</li> 234 <li>Generation of Makefiles and scripts for running logic synthesis tools</li> 235 </ul> 236 <li>Hardware operator library (Configurable multipliers, Logarithm functions, Variable shifters, Dividers and modulo extractors)</li> 237 <li>TODO list <b>[UPDATED: 2013-02-05]</b></li> 238 <ul> 239 <li>New C frontend</li> 240 <li>Multi-port memory synthesis (external tool available)</li> 241 <li>Access to global data from any procedure. Currently only the "root" procedure can access globals</li> 242 <li>Support of dynamically allocated data</li> 243 <li>Support of record data types (WIP: supported by new C frontend under development)</li> 244 <li>List scheduling with operation chaining optimizations</li> 245 <li>Graph-based optimization engine (WIP: prototype development)</li> 246 <li>Enhanced data flow analysis</li> 247 <li>Recursive procedure support <b>[UPDATE: currently supported in the C backend]</b></li> 248 </ul> 249 </ul> 250 </p> 251 252 </font> 253 254 </ol> 255 256 <br> 257 258 <br><hr size="1"><br> 259 260 <ul> 261 262 <a name="howitworks"> 263 264 <font class="plain_text">How it works</font> 265 266 </ul> 267
268 <ol> 269 270 <font class="small_text"> 271 272 <p> 273 The following figure gives an internal view to the process flow of HercuLeS. 274 </p> 275 276 <p align="center"> 277 278 <IMG src="hlsflow.dot.png" width="100%"><br><br> 279 280 </p> 281 282 <p> 283 The user of HercuLeS must provide two input files: 284 <ul> 285 <li>design.nac: A NAC program translation unit providing the entire application. The root 286 procedure must be named "design"</li> 287 <li>design_test_data.txt: Input/output reference values for use by the automatically-generated 288 testbench</li> 289 </ul> 290 Then, <b>nac2cdfg</b> generates several files:<br> 291 <ul> 292 <li>design.dot, subdes1.dot, ..., subdesn.dot: The Graphviz CDFGs for the root procedure 293 and all other procedures in the NAC program.</li> 294 <li>main.c, main.h, ansic.mk: Files generated for running an ANSI C simulation. 295 ansic.mk is an automatically-generated Makefile.</li> 296 <li>design_nac.c, subdes1_nac.c, ..., subdesn_nac.c: ANSI C backend files providing 297 C implementations of all procedures in the translation unit, generated directly from NAC. 298 They are used in the C simulations.</li> 299 <li>design_pkg.vhd: VHDL package incorporating the components for all NAC procedures.</li> 300 <li>design_cdt_pkg.vhd: VHDL package incorporating definitions of compound data types (arrays).</li> 301 </ul> 302 Following this, there exist two possible flows; one for the generation and simulation of synthesizable 303 RTL VHDL for the NAC program, and one for a C simulation.<br> 304 The C simulation flow proceeds by invoking the ansic.mk makefile by running:<br> 305 <tt>make -f ansic.mk</tt><br> 306 from the command line. This produces a main.exe executable specification (e.g. on Windows/Cygwin). 307 Then, the executable is run:<br> 308 <tt>./main</tt><br> 309 and output is produced at the command prompt.<br> 310 The VHDL flow involves processing all CDFG (.dot) files by <b>cdfg2hdl</b>, the actual backend tool 311 of HercuLeS. <b>cdfg2hdl</b> generates several files: 312 <ul> 313 <li>design.vhd, subdes1.vhd, ..., subdesn.vhd: Synthesizable RTL VHDL for the root procedure 314 and all other procedures in the NAC program.</li> 315 <li>ram.vhd: VHDL model of a dual-port synchronous read RAM for block RAM inference. 316 It is only used if block RAM mapping is enabled.</li> 317 <li>design_tb.vhd: The automatically-generated self-checking testbench.</li> 318 <li>design.mk: Makefile for running a GHDL simulation.</li> 319 <li>design.do: Modelsim do macro file for running a Modelsim simulation.</li> 320 <li>design.sh: Bash shell script initiating either a GHDL or Modelsim simulation.</li> 321 </ul> 322 Finally, the design.sh script is run from the command line:<br> 323 <tt>./design.sh</tt><br> 324 This produces a text file (design_alg_test_results.txt) providing diagnostic 325 output from a simulation run. Output to the command prompt for any internal 326 program variable, procedure argument, etc can be produced by using the "print" 327 NAC operation. A "print" is mapped to a VHDL "assert" construct or a C standard 328 library "printf".<br> 329 Also, a VCD (design_fsmd.vcd) or GHW (design_fsmd.ghw) waveform file can be 330 generated for viewing with <a href="http://sourceforge.net/projects/gtkwave">GTKwave</a>. 331 Windows binaries for GTKwave can be found <a href="http://www.dspia.com/gtkwave.html">here</a>. 332 </p> 333 </font> 334 </ol> 335 336 <br> 337 338 <br><hr size="1"><br> 339 340 <ul> 341 342 <a name="nac"> 343 344 <font class="plain_text">The NAC programming language</font> 345 346 </ul> 347 348 <ol> 349 350 <font class="small_text"> 351 352 <p> 353 NAC is an extensible, bit-accurate, typed-assembly language. NAC provides arbitrary <b>n</b>-to-<b>m</b> 354 operation mappings, enforcing a single format for all operations, and 355 bit-accurate data types. It supports scalar, single-dimensional array and streamed I/O procedure 356 arguments. NAC statements are labels, n-address instructions or procedure calls. 357 </p> 358 359 <p> 360 The current version (0.0.4) of the NAC programming language manual can be found 361 <a href="./nac-refman.html">here</a> in HTML form and can be downloaded from 362 <a href="./nac-refman.pdf">here</a> as a PDF file. 363 </p> 364 365 </font> 366 367 </ol> 368 369 <br> 370 371 <br><hr size="1"><br> 372 373 <ul> 374 375 <a name="gimple2nac"> 376 377 <font class="plain_text">gimple2nac: A prototype C frontend based on GCC GIMPLE</font> 378 379 </ul> 380 381 <ol> 382 383 <font class="small_text"> 384 385 <p> 386 An ANSI C frontend, namely <b>gimple2nac</b> is under development for translating 387 GIMPLE dumps from GCC compilation to NAC translation units. It is currently in usable 388 state, provided that the current liminations of the GCC GIMPLE front end infrastru
388cture 389 are accounted. The GIMPLE front end is under heavy development; a future release of GCC 390 will support the final textual GIMPLE grammar). 391 The <a href="http://gcc.gnu.org/wiki/GimpleFrontEnd">gimple-front-end</a> 392 branch is aiming to this purpose: to provide a fixed textual IR. 393 </p> 394 395 <p> 396 The textual GIMPLE IR will bare some similarities to the current format of GIMPLE dumps. 397 As input, gimple2nac currently accepts the non-official grammar of GIMPLE files with the 398 .004t.gimple suffix.<br><br> 399 I am currently writing a document highlighting issues with code generation from 400 GIMPLE dumps. You can find it 401 <a href="./gimple-notes.html">here</a> in HTML form and can be downloaded from 402 <a href="./gimple-notes.pdf">here</a> as a PDF file. 403 </p> 404 405 <p> 406 <b>gimple2nac</b> will be released under GPL, version 3 when the gimple-front-end branch 407 will be merged to GCC mainline, and the corresponding grammar and semantic changes 408 will propagate to my GIMPLE-to-NAC translator. 409 </p> 410 411 </font> 412 413 </ol> 414 415 <br> 416 417 <br><hr size="1"><br> 418 419 <ul> 420 421 <a name="nacexamples"> 422 423 <font class="plain_text">Complete examples for the NAC to VHDL flow</font> 424 425 </ul> 426 427 <ol> 428 429 <font class="small_text"> 430 431 <p> 432 The following set of examples illustrates the high-level synthesis of NAC programs. 433 They have been generated with SSA (Static Single Assignment) disabled and using the 434 sequential scheduler. The examples have been selected so that the hardware operator 435 library is not required. In the future, an obfuscated or encrypted version of the 436 library will be included.<br> 437 A self-contained ZIP file with these examples is available: 438 <a href="./nac-examples.zip">nac-examples.zip</a><br> 439 To run a simulation from this package, unzip the package, cd to the corresponding directory (e.g. fibo) 440 and run:<br> 441 <tt>./fibo.sh</tt><br> 442 provided that you have GHDL installed on your system. You will also need a Windows/Cygwin 443 installation or gnuwin32 versions of standard Unix utilities: make, bash.<br> 444 The simulation will need two files providing some IEEE extension functions/procedures. 445 They are required only for running the simulations. These files are provided in the 446 00contrib subdirectory.<br> 447 Each example (e.g. NAC program "design.nac") includes the following source files: 448 <ul type="square"> 449 <li>NAC program: <b>design.nac</b></li> 450 <li>Reference vectors: <b>design_test_data.txt</b></li> 451 </ul><br> 452 and the following generated files: 453 <ul type="square"> 454 <li>VHDL design: <b>design.vhd</b> for the root procedure and any other VHDL files for each one of the called procedures 455 (from root or from lower in the call tree hierarchy).</li> 456 <li>Testbench: <b>design_tb.vhd</b></li> 457 <li>CDFG visualization: <b>design.dot.png</b></li> 458 <li>CFG visualization: <b>design_cfg.dot.png</b></li> 459 <li>GHDL Makefile: <b>design.mk</b></li> 460 <li>Bash script for VHDL simulation with GHDL: <b>design.sh</b></li> 461 <li>Diagnostic output: <b>design_alg_test_results.txt</b> (only in the ZIP file).</li> 462 </ul><br> 463 </p> 464 465 <p> 466 The files included in <a href="./nac-examples.zip">nac-examples.zip</a> are also 467 available for separate viewing from here: 468 <ul type="square"> 469 <li><b>loop1</b> (a single loop for-loop counting from 0 to a configurable limit. The easiest example)<br> 470 Files: 471 <a href="./nac/loop1/loop1.nac">loop1.nac</a>, 472 <a href="./nac/loop1/loop1_test_data.txt">loop1_test_data.txt</a>, 473 <a href="./nac/loop1/loop1.vhd">loop1.vhd</a>, 474 <a href="./nac/loop1/loop1_tb.vhd">loop1_tb.vhd</a>, 475 <a href="./nac/loop1/loop1.dot.png">loop1 CDFG</a>, 476 <a href="./nac/loop1/loop1_cfg.dot.png">loop1 CFG</a>, 477 <a href="./nac/loop1/loop1.mk">Makefile for GHDL simulation of loop1</a>, 478 <a href="./nac/loop1/loop1.sh">Bash script for automating the simulation of loop1</a>.</li> 479 <li><b>fibo</b> (iterative version of Fibonacci sequence generation)<br> 480 Files: 481 <a href="./nac/fibo/fibo.nac">fibo.nac</a>, 482 <a href="./nac/fibo/fibo_test_data.txt">fibo_test_data.txt</a>, 483 <a href="./nac/fibo/fibo.vhd">fibo.vhd</a>, 484 <a href="./nac/fibo/fibo_tb.vhd">fibo_tb.vhd</a>, 485 <a href="./nac/fibo/fibo.dot.png">fibo CDFG</a>, 486 <a href="./nac/fibo/fibo_cfg.dot.png">fibo CFG</a>, 487 <a href="./nac/fibo/fibo.mk">Makefile for GHDL simulation of fibo</a>, 488 <a href="./nac/fibo/fibo.sh">Bash script for automating the simulation of fibo</a>.</li> 489 <li><b>divider</b> (sequential divider producing both quotient and remainder)<br> 490 Files: 491 <a href="./nac/divider/divider.nac">divider.nac</a>, 492 <a href="./nac/divider/divider_test_data.txt">divider_test_data.txt</a>, 493 <a href="./nac/divider/divider.vhd">divider.vhd</a>, 494 <a href="./nac/divider/divider_tb.vhd">divider_tb.vhd</a>, 495 <a href="./nac/divider/divider.dot.png">divider CDFG</a>, 496 <a href="./nac/divider/divider_cfg.dot.png">divider CFG</a>, 497 <a href="./nac/divider/divider.mk">Makefile for GHDL simulation of divider</a>, 498 <a href="./nac/divider/divider.sh">Bash script for automating the simulation of divider</a>.</li> 499 <li><b>isqrt</b> (integer square root calculation)<br> 500 Files: 501 <a href="./nac/isqrt/isqrt.nac">isqrt.nac</a>, 502 <a href="./nac/isqrt/isqrt_test_data.txt">isqrt_test_data.txt</a>, 503 <a href="./nac/isqrt/isqrt.vhd">isqrt.vhd</a>, 504 <a href="./nac/isqrt/isqrt_tb.vhd">isqrt_tb.vhd</a>, 505 <a href="./nac/isqrt/isqrt.dot.png">isqrt CDFG</a>, 506 <a href="./nac/isqrt/isqrt_cfg.dot.png">isqrt CFG</a>, 507 <a href="./nac/isqrt/isqrt.mk">Makefile for GHDL simulation of isqrt</a>, 508 <a href="./nac/isqrt/isqrt.sh">Bash script for automating the simulation of isqrt</a>.</li> 509 </ul> 510 </ul> 511 </p> 512 513 </font> 514 515 </ol> 516 517 <br> 518 519 <br><hr size="1"><br> 520 521 <ul> 522 523 <a name="ansicexamples"> 524 525 <font class="plain_text">Complete examples for the ANSI C to VHDL flow</font> 526 527 </ul> 528 529 <ol> 530 531 <font class="small_text"> 532 533 <p> 534 The following set of examples illustrates the high-level synthesis of ANSI C programs. 535 The overall process involves translation of C programs to GIMPLE, followed 536 by processing from gimple2nac, nac2cdfg, and cdfg2hdl.<br> 537 This set of examples has been generated
537with SSA (Static Single Assignment) enabled, using 538 the ASAP scheduler and with block RAMs enabled.<br> 539 A self-contained ZIP file with these examples is available: 540 <a href="./ansic-examples.zip">ansic-examples.zip</a><br> 541 gcc-4.5.1 has been used for producing the .gimple files. From these files, the 542 corresponding .nac is generated with "gimple2nac". The same rules apply (as above) 543 for running a GHDL simulation.<br> 544 The sieve design requires a full multiplier. An implementation of the mul operator 545 is provided in file operpack_ieee.vhd. Its implementation is subject to change in 546 the future (e.g. for better performance). Further, the simulation will need two files providing 547 some IEEE extension functions/procedures. 548 They are required only for running the simulations. These files are provided in the 549 00contrib subdirectory.<br> 550 Each example (e.g. C program "design_generic.c") includes the following source files: 551 <ul type="square"> 552 <li>ANSI C program: <b>design_generic.c</b></li> 553 <li>Reference vectors: <b>design_test_data.txt</b></li> 554 </ul><br> 555 and the following generated files: 556 <ul type="square"> 557 <li>GIMPLE file: <b>design_generic.c.004t.gimple</b></li> 558 <li>NAC file: <b>design.nac</b></li> 559 <li>VHDL design: <b>design.vhd</b> for the root procedure and any other VHDL files for each one of the called procedures 560 (from root or from lower in the call tree hierarchy).</li> 561 <li>Testbench: <b>design_tb.vhd</b></li> 562 <li>CDFG visualization: <b>design.dot.png</b></li> 563 <li>CFG visualization: <b>design_cfg.dot.png</b></li> 564 <li>GHDL Makefile: <b>design.mk</b></li> 565 <li>Bash script for VHDL simulation with GHDL: <b>design.sh</b></li> 566 <li>Diagnostic output: <b>design_alg_test_results.txt</b> (only in the ZIP file).</li> 567 <li><b>NOTE:</b> For the case of the "sieve" example, more design files are generated, since it 568 comprises of two procedures: sieve (the root procedure) and isqrt (which is called by root). 569 </ul><br> 570 </p> 571 572 <p> 573 The files included in <a href="./ansic-examples.zip">ansic-examples.zip</a> are also 574 available for separate viewing from here: 575 <ul type="square"> 576 <li><b>fibo</b> (iterative version of Fibonacci sequence generation)<br> 577 Files: 578 <a href="./ansic/fibo/fibo_generic.c">Input C file for fibo</a>, 579 <a href="./ansic/fibo/fibo_generic.c.004t.gimple">GIMPLE file for fibo generated by gcc</a>, 580 <a href="./ansic/fibo/fibo.nac">fibo.nac</a>, 581 <a href="./ansic/fibo/fibo_test_data.txt">fibo_test_data.txt</a>, 582 <a href="./ansic/fibo/fibo.vhd">fibo.vhd</a>, 583 <a href="./ansic/fibo/fibo_tb.vhd">fibo_tb.vhd</a>, 584 <a href="./ansic/fibo/fibo.dot.png">fibo CDFG</a>, 585 <a href="./ansic/fibo/fibo_cfg.dot.png">fibo CFG</a>, 586 <a href="./ansic/fibo/fibo.mk">Makefile for GHDL simulation of fibo</a>, 587 <a href="./ansic/fibo/fibo.sh">Bash script for automating the simulation of fibo</a>.</li> 588 <li><b>gcd</b> (greatest common divisor)<br> 589 Files: 590 <a href="./ansic/gcd/gcd_generic.c">Input C file for gcd</a>, 591 <a href="./ansic/gcd/gcd_generic.c.004t.gimple">GIMPLE file for gcd generated by gcc</a>, 592 <a href="./ansic/gcd/gcd.nac">gcd.nac</a>, 593 <a href="./ansic/gcd/gcd_test_data.txt">gcd_test_data.txt</a>, 594 <a href="./ansic/gcd/gcd.vhd">gcd.vhd</a>, 595 <a href="./ansic/gcd/gcd_tb.vhd">gcd_tb.vhd</a>, 596 <a href="./ansic/gcd/gcd.dot.png">gcd CDFG</a>, 597 <a href="./ansic/gcd/gcd_cfg.dot.png">gcd CFG</a>, 598 <a href="./ansic/gcd/gcd.mk">Makefile for GHDL simulation of gcd</a>, 599 <a href="./ansic/gcd/gcd.sh">Bash script for automating the simulation of gcd</a>.</li> 600 <li><b>linedraw</b> (Bresenham's line drawing algorithm. Illustrates the use of streaming outputs)<br> 601 Files: 602 <a href="./ansic/linedraw/linedraw_generic.c">Input C file for linedraw</a>, 603 <a href="./ansic/linedraw/linedraw_generic.c.004t.gimple">GIMPLE file for linedraw generated by gcc</a>, 604 <a href="./ansic/linedraw/linedraw.nac">linedraw.nac</a>, 605 <a href="./ansic/linedraw/linedraw_test_data.txt">linedraw_test_data.txt</a>, 606 <a href="./ansic/linedraw/linedraw.vhd">linedraw.vhd</a>, 607 <a href="./ansic/linedraw/linedraw_tb.vhd">linedraw_tb.vhd</a>, 608 <a href="./ansic/linedraw/linedraw.dot.png">linedraw CDFG</a>, 609 <a href="./ansic/linedraw/linedraw_cfg.dot.png">linedraw CFG</a>, 610 <a href="./ansic/linedraw/linedraw.mk">Makefile for GHDL simulation of linedraw</a>, 611 <a href="./ansic/linedraw/linedraw.sh">Bash script for automating the simulation of linedraw</a>.</li> 612 <li><b>sieve</b> (sieve of Eratosthenes. Illustrates the use of global arrays and procedure calls)<br> 613 Files: 614 <a href="./ansic/sieve/sieve_generic.c">Input C file for sieve</a>, 615 <a href="./ansic/sieve/sieve_generic.c.004t.gimple">GIMPLE file for sieve generated by gcc</a>, 616 <a href="./ansic/sieve/sieve.nac">sieve.nac</a>, 617 <a href="./ansic/sieve/sieve_test_data.txt">sieve_test_data.txt</a>, 618 <a href="./ansic/sieve/sieve_cdt_pkg.vhd">VHDL package containing array data type definitions for sieve</a>, 619 <a href="./ansic/sieve/ram.vhd">RAM memory model for block RAM inference</a>, 620 <a href="./ansic/sieve/sieve.vhd">sieve.vhd</a>, 621 <a href="./ansic/sieve/isqrt.vhd">isqrt.vhd</a>, 622 <a href="./ansic/sieve/sieve_tb.vhd">sieve_tb.vhd</a>, 623 <a href="./ansic/sieve/sieve.dot.png">sieve CDFG</a>, 624 <a href="./ansic/sieve/sieve_cfg.dot.png">sieve CFG</a>, 625 <a href="./ansic/sieve/isqrt.dot.png">isqrt CDFG</a>, 626 <a href="./ansic/sieve/isqrt_cfg.dot.png">isqrt CFG</a>, 627 <a href="./ansic/sieve/sieve.mk">Makefile for GHDL simulation of sieve</a>, 628 <a href="./ansic/sieve/sieve.sh">Bash script for automating the simulation of sieve</a>.</li> 629 </ul> 630 </ul> 631 </p> 632 633 </font> 634 635 </ol> 636 637 <br> 638 639 <br><hr size="1"><br> 640 641 <ul> 642 643 <a name="downloads"> 644 645 <font class="plain_text">Other downloads</font> 646 647 </ul> 648 649 <ol> 650 651 <br> 652 653 <font class="small_text"> 654 <ol type="square"> 655 <li>A recent (December 2012) <a href="./hlstool_pres.pdf">presentation</a> of the HercuLeS hardware compiler.</li> 656 <li>The HercuLeS reference manual in <a href="../hercules-reference-manual/hercules-refman.pdf"><b>PDF</b></a> and 657 <a href="../hercules-reference-manual/hercules-refman.html"><b>HTML</b>.</a> Chapter 8 describes the HercuLeS GUI</li> 658 <li>HercuLeS feature matrix in <a href="./hercules-feature-matrix.pdf"><b>PDF</b></a> and <a href="./hercules-feature-matrix.html"><b>HTML</b></a></li> 659 <li><a href="./nac.ebnf">EBNF NAC grammar</a></li> 660 <li><a href="./nac.y">NAC yacc/bison grammar</a></li> 661 <li><a href="./nac.l">NAC lex/flex scanner</a></li> 662 <li><a href="./nacparser-110707.zip">Basic flex/bison parser for NAC (nacparser)</a></li> 663 <li><a href="./nac.gold">NAC grammar for the GOLD Parsing System</a>. 664 The <a href="http://www.devincook.com/goldparser/">GOLD Parsing System</a> is a parser generation framework.</li> 665 <li><a href="./nac.grm">TXL grammar for NAC</a>. <a href="http://www.txl.ca">TXL</a> is a source transformation language.</li> 666 <li><a href="./nacparser.txl">TXL pretty printer for NAC</a></li> 667 <li>[OLD] Sample test sets of software applications. The set include binaries generated by GHDL 668 running on Fedora 8. These binaries are self-contained and can be run under any re
668cent Linux distribution. 669 Feel <b>FREE</b> to download this <b>OLD</b> demo: 670 <a href="../misc/hls-demo-linux-0.0.1.tar.gz"><b>hls-demo-linux-0.0.1.tar.gz</b></a><br> 671 You should run this from a Linux command prompt. A slightly-different 672 version (with interpreted and not built models) was also tested successfully on Cygwin/Windows XP.<br> 673 [<b>UPDATED</b>: 05-June-2010]<br></li> 674 <li>Preliminary documentation for <b>nac2cdfg</b> in 675 <a href="./nac2cdfg.html"><b>HTML</b></a> and <a href="./nac2cdfg.pdf"><b>PDF</b></a> formats (covering command-line options).</li> 676 <li>Preliminary documentation for <b>cdfg2hdl</b> in 677 <a href="./cdfg2hdl.html"><b>HTML</b></a> and <a href="./cdfg2hdl.pdf"><b>PDF</b></a> formats (covering command-line options).</li> 678 <li>[TBR] A complete example of a multi-function CORDIC.</li> 679 <li>[TBR] Performance comparison to other high-level synthesis tools.</li> 680 <li>[TBR] Self-contained peephole optimizer for NAC programs.</li> 681 </ol> 682 </font> 683 </ol> 684 685 <br><hr size="1"> 686 687 <br> 688<!-- 689 <ul> 690 691 <a name="undisclosed"> 692 693 <font class="plain_text">Undisclosed information</font> 694 695 </ul> 696 697 <ol> 698 699 <font class="small_text"> 700 701 <p> 702 <ul> 703 <li>The exact format of the Graphviz CDFG with user-defined attributes.</li> 704 <li>The full hardware operator library. Specifically the used implementations of 705 multipliers and dividers (extraction of quotient and remainder/modulus) are not 706 disclosed.</li> 707 <li>The <b>nac2cdfg</b> and <b>cdfg2hdl</b> source code and API.</li> 708 </ul> 709 </p> 710 711 </font> 712 713 </ol> 714 715 <br> 716--> 717 <br><hr size="1"><br> 718 719 <font class="small_text"> 720 Updated by <a href="mailto:[email protected]">Nikolaos Kavvadias</a> on <b>August 23, 2016</b><br> 721 Previous versions: June 06, 2013 / February 05, 2013 / February 02, 2012 / October 31, 2011. 722 </font> 723 724 <br> 725 726 </td> 727 728 </tr> 729 730</table> 731 732<br><hr size="1"> 733 <tr> 734 <td align="center"> 735 <a href="http://s09.flagcounter.com/more/Geu"><img src="http://s09.flagcounter.com/count/Geu/bg=FFFFFF/txt=000000/border=CCCCCC/columns=4/maxflags=20/viewers=3/labels=0/pageviews=1/" alt="free counters" border="0"></a> 736 </td> 737 </tr> 738 739</body> 740 741</html>
Line numbers count LF bytes from the start of the resource, as the search results do. Vendor segments are library code the classifier recognised; they are stored but not indexed. Bytes are shown as Latin1 characters, one per byte.