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629This localized architecture is well suited to chiplet processors, AI accelerators, HPC devices, FPGAs, and logic-plus-HBM packages. It combines the routing density of silicon at critical die interfaces with the larger routing area, power distribution, and mechanical support provided by an organic package substrate.</p> 630 631 632 633<figure class="wp-block-image"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-technology-hero.jpg" alt="Conceptual EMIB package showing local silicon bridge, logic dies, substrate and BGA connections"/></figure> 634 635 636 637<h2 class="wp-block-heading">Key Takeaways</h2> 638 639 640 641<ul class="wp-block-list"> 642<li>EMIB stands for <strong><a href="https://www.bestpcbs.com/blog/2026/09/emib/">Embedded Multi-die Interconnect Bridge</a></strong>, a 2.5D packaging technology that places small silicon bridges inside the package substrate for high-density die-to-die connections.</li> 643 644 645 646<li>Unlike a large silicon interposer, EMIB uses silicon only at selected interfaces where fine-pitch routing is required.</li> 647 648 649 650<li>The silicon bridge connects adjacent logic dies, chiplets, or HBM through short, dense interconnects while the surrounding package substrate handles broader routing and power distribution.</li> 651 652 653 654<li>EMIB manufacturing combines silicon bridge fabrication with cavity formation, bridge embedding, substrate build-up, fine routing, die attach, and package testing.</li> 655 656 657 658<li>EMIB, EMIB-M, and EMIB-T share the localized bridge concept but add different electrical capabilities, including integrated capacitors or TSV-enabled vertical connections.</li> 659 660 661 662<li>EMIB and <a href="https://www.bestpcbs.com/blog/2026/09/cowos-l/">CoWoS-L</a> both use localized silicon interconnect structures, although their surrounding routing media and overall package architectures differ.</li> 663</ul> 664 665 666 667<h2 class="wp-block-heading">What Is EMIB?</h2> 668 669 670 671<p>EMIB is a localized silicon-bridge packaging architecture that provides high-density electrical connections between adjacent dies. A small piece of silicon with fine metal routing is embedded in the package substrate beneath the edges of two neighboring dies.</p> 672 673 674 675<p>Fine-pitch bumps connect both dies to this silicon bridge. Signals can then cross the die boundary through short, dense routing without requiring a large silicon interposer underneath the complete package.</p> 676 677 678 679<p>A typical EMIB package can include:</p> 680 681 682 683<ul class="wp-block-list"> 684<li>logic dies or compute chiplets;</li> 685 686 687 688<li>HBM stacks;</li> 689 690 691 692<li>one or more embedded silicon bridges;</li> 693 694 695 696<li>fine-pitch die-to-bridge connections;</li> 697 698 699 700<li>an organic package substrate;</li> 701 702 703 704<li>copper power and signal routing;</li> 705 706 707 708<li>BGA connections to the <a href="https://www.bestpcbs.com/design-guide/index.htm">system PCB</a>.</li> 709</ul> 710 711 712 713<p>The bridge is used where routing density is highest. Lower-density signals, power, ground, and package-level connections can remain in the surrounding substrate, allowing different parts of the package to use interconnect structures suited to their actual electrical requirements.</p> 714 715 716 717<h2 class="wp-block-heading">What Is an EMIB Substrate?</h2> 718 719 720 721<p>An EMIB substrate is a package substrate containing one or more embedded silicon bridges beneath selected die interfaces. It still performs the normal functions of an advanced IC package substrate, but adds localized regions capable of much finer routing.</p> 722 723 724 725<p>The main structures include:</p> 726 727 728 729<div class="wp-block-table"> 730<table> 731<tbody> 732<tr> 733<td><strong>Structure</strong></td> 734<td><strong>Main Function</strong></td> 735</tr> 736<tr> 737<td>Organic package substrate</td> 738<td>Broad signal routing, power distribution, and mechanical support</td> 739</tr> 740<tr> 741<td>Embedded silicon bridge</td> 742<td>High-density die-to-die routing</td> 743</tr> 744<tr> 745<td>Build-up layers</td> 746<td>Connect the bridge to surrounding substrate routing</td> 747</tr> 748<tr> 749<td>Fine-pitch bumps</td> 750<td>Connect dies to the bridge</td> 751</tr> 752<tr> 753<td>Copper vias and planes</td> 754<td>Carry power, ground, and package-level signals</td> 755</tr> 756<tr> 757<td>BGA solder balls</td> 758<td>Connect the package to the system PCB</td> 759</tr> 760</tbody> 761</table> 762</div> 763 764 765 766<p>The key feature is localization. Only the interfaces that need very high routing density use silicon, while the rest of the package can rely on organic build-up technology.</p> 767 768 769 770<p>This is useful in heterogeneous packages because routing requirements are rarely uniform. A compute die may need thous
770ands of closely spaced connections to HBM, while other interfaces can operate with much wider routing pitches.</p> 771 772 773 774<h2 class="wp-block-heading">How Does EMIB Work?</h2> 775 776 777 778<p>EMIB works by routing high-speed signals through an embedded silicon bridge positioned directly below the edges of neighboring dies. Fine-pitch bumps connect each die to the bridge, and the bridge’s metal layers carry signals across the gap.</p> 779 780 781 782<p>The signal path can be simplified as:</p> 783 784 785 786<ul class="wp-block-list"> 787<li><strong>Die A â Fine-Pitch Bumps â Silicon Bridge</strong></li> 788 789 790 791<li><strong>Silicon Bridge â Fine-Pitch Bumps â Die B</strong></li> 792</ul> 793 794 795 796<p>This architecture is suitable for several high-bandwidth connections, including:</p> 797 798 799 800<ul class="wp-block-list"> 801<li>logic-to-logic;</li> 802 803 804 805<li>compute-to-I/O;</li> 806 807 808 809<li>logic-to-HBM;</li> 810 811 812 813<li>accelerator-to-memory;</li> 814 815 816 817<li>chiplet-to-chiplet interfaces.</li> 818</ul> 819 820 821 822<p>The surrounding organic substrate does not need to match the bridge’s routing density. It can handle broader signal paths, power distribution, and connections toward the BGA, which keeps the high-density silicon region focused on the die boundaries where it provides the greatest value.</p> 823 824 825 826<figure class="wp-block-image"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-signal-path.jpg" alt="Signal routing between adjacent dies through a local silicon bridge"/></figure> 827 828 829 830<h2 class="wp-block-heading">Why Does EMIB Use a Local Silicon Bridge?</h2> 831 832 833 834<p>EMIB uses a local silicon bridge because high-density routing is usually required only at specific die interfaces rather than across the entire package. A localized bridge places silicon exactly where the fine-pitch interconnect is needed.</p> 835 836 837 838<p>This architecture provides several practical benefits:</p> 839 840 841 842<ul class="wp-block-list"> 843<li>silicon area is concentrated at critical interfaces;</li> 844 845 846 847<li>neighboring dies communicate through short electrical paths;</li> 848 849 850 851<li>organic routing remains available across most of the package;</li> 852 853 854 855<li>bridge placement can follow the actual chiplet floorplan;</li> 856 857 858 859<li>several bridges can be distributed across a large package;</li> 860 861 862 863<li>package size can grow without requiring one equally large silicon interposer.</li> 864</ul> 865 866 867 868<p>For example, a package containing multiple compute chiplets and HBM stacks may need very dense routing only between each logic die and its neighboring memory. Local bridges allow those interfaces to use silicon-level routing while the rest of the substrate remains optimized for package-scale connections.</p> 869 870 871 872<h2 class="wp-block-heading">What Is the EMIB Process Flow?</h2> 873 874 875 876<p>The EMIB process flow combines silicon bridge fabrication, substrate cavity preparation, bridge embedding, build-up routing, and final multi-die assembly. Exact production details depend on the package generation, but the general manufacturing sequence follows the same structure.</p> 877 878 879 880<ol class="wp-block-list"> 881<li><strong>Silicon bridge fabrication</strong> Fine metal routing is fabricated on the silicon bridge using semiconductor-compatible processing.</li> 882 883 884 885<li><strong>
885Substrate cavity formation</strong> A recessed region is prepared at the location where the bridge will be embedded.</li> 886 887 888 889<li><strong>Bridge placement</strong> The silicon bridge is accurately positioned inside the package substrate.</li> 890 891 892 893<li><strong>Dielectric build-up</strong> Organic dielectric layers are formed around and above the embedded bridge.</li> 894 895 896 897<li><strong>Copper routing formation</strong> Copper traces and vias connect the bridge region with the broader substrate routing.</li> 898 899 900 901<li><strong>Fine-pitch interface preparation</strong> Pads and bump structures are prepared above the bridge for die attachment.</li> 902 903 904 905<li><strong>Die attach</strong> Logic dies, chiplets, HBM, or other components are mounted on the substrate.</li> 906 907 908 909<li><strong>Package assembly and test</strong> Underfill, mechanical reinforcement, electrical inspection, and reliability testing complete the package.</li> 910</ol> 911 912 913 914<p>Bridge alignment is especially important because the embedded structure has to register with both the substrate routing below and the fine-pitch die connections above. Smaller interconnect pitches reduce the available margin for dimensional variation.</p> 915 916 917 918<figure class="wp-block-image"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-process-flow.jpg" alt="Four conceptual EMIB integration stages from cavity preparation to assembly and testing"/></figure> 919 920 921 922<h2 class="wp-block-heading">What Are the Main Advantages of EMIB?</h2> 923 924 925 926<p>The main advantage of EMIB is that it provides silicon-level routing density without requiring a package-wide silicon interposer. This makes the architecture attractive when only selected interfaces need extremely dense connections.</p> 927 928 929 930<p>Key advantages include:</p> 931 932 933 934<ul class="wp-block-list"> 935<li><strong>High interconnect density:</strong> fine silicon routing supports wide die-to-die interfaces.</li> 936 937 938 939<li><strong>Short signal paths:</strong> adjacent dies communicate through compact local bridges.</li> 940 941 942 943<li><strong>Localized silicon usage:</strong> silicon is used mainly where its routing capability is required.</li> 944 945 946 947<li><strong>Heterogeneous integration:</strong> logic, memory, I/O, and accelerator dies can share one package.</li> 948 949 950 951<li><strong>Flexible floorplanning:</strong> bridge locations can follow chiplet placement.</li> 952 953 954 955<li><strong>Package scalability:</strong> multiple bridge regions can be distributed across a larger package.</li> 956 957 958 959<li><strong>Process-node flexibility:</strong> individual dies can use fabrication nodes suited to their functions.</li> 960</ul> 961 962 963 964<p>This is particularly useful for chiplet architectures. Compute logic can use an advanced node, while I/O, analog, or supporting functions can use other processes without giving up high-bandwidth die-to-die communication.</p> 965 966 967 968<h2 class="wp-block-heading">What Are the Main EMIB Design and Manufacturing Challenges?</h2> 969 970 971 972<p>EMIB manufacturing must integrate fine-feature silicon structures into a much larger organic substrate while maintaining alignment, planarity, electrical performance, and long-term reliability.</p> 973 974 975 976<p>The main challenges include:</p> 977 978 979 980<ul class="wp-block-list"> 981<li><strong>Bridge placement accuracy:</strong> the silicon bridge must align precisely with fine-pitch die interfaces.</li> 982 983 984 985<li><strong>Substrate warpage:</strong> silicon, copper, dielectric, and molding materials expand differently during thermal cycling.</li> 986 987 988 989<li><strong>Coplanarity:</strong> uneven surfaces can affect die attach and fine-pitch joint quality.</li> 990 991 992 993<li><strong>Microbump reliability:</strong> small joints experience thermal and mechanical stress during assembly and operation.</li> 994 995 996 997<li><strong>Signal integrity:</strong> impedance, crosstalk, return paths, and interconnect discontinuities require careful control.</li> 998 999 1000 1001<li><strong>Thermal-mechanical stress:</strong> large logic dies and HBM stacks can create strong temperature gradients.</li> 1002 1003 1004 1005<li><strong>Yield management:</strong> a late-stage defect may affect several expensive known-good dies in the same package.</li> 1006</ul> 1007 1008 1009 1010<p>These issues become more difficult as package size increases. Larger substrates have tighter requirements for dimensional stability because even small material movement can affect bridge registration and fine-pitch assembly across the package.</p> 1011 1012 1013 1014<h2 class="wp-block-heading">EMIB vs Silicon Interposer: What Is the Difference?</h2> 1015 1016 1017 1018<p>EMIB uses small localized silicon bridges, while a conventional silicon-interposer package uses a much larger continuous silicon rout
1018ing layer beneath multiple dies. Both provide fine-pitch interconnection, but they distribute the high-density silicon very differently.</p> 1019 1020 1021 1022<div class="wp-block-table"> 1023<table> 1024<tbody> 1025<tr> 1026<td><strong>Feature</strong></td> 1027<td><strong>EMIB</strong></td> 1028<td><strong>Silicon Interposer</strong></td> 1029</tr> 1030<tr> 1031<td>Silicon routing area</td> 1032<td>Local bridge regions</td> 1033<td>Large continuous area</td> 1034</tr> 1035<tr> 1036<td>Position</td> 1037<td>Embedded in package substrate</td> 1038<td>Beneath multiple dies</td> 1039</tr> 1040<tr> 1041<td>Fine routing coverage</td> 1042<td>Selected die interfaces</td> 1043<td>Broad interposer area</td> 1044</tr> 1045<tr> 1046<td>Package-level routing</td> 1047<td>Mainly organic substrate</td> 1048<td>Interposer + substrate</td> 1049</tr> 1050<tr> 1051<td>Conventional bridge TSVs</td> 1052<td>Not required</td> 1053<td>Common in silicon interposers</td> 1054</tr> 1055<tr> 1056<td>Scaling approach</td> 1057<td>Add localized bridges</td> 1058<td>Increase interposer area</td> 1059</tr> 1060</tbody> 1061</table> 1062</div> 1063 1064 1065 1066<p>A full silicon interposer is useful when dense routing is required across a broad die complex. EMIB is more localized, making it suitable when the highest routing density is concentrated along specific die boundaries.</p> 1067 1068 1069 1070<p>The appropriate architecture depends on the package floorplan, number of dies, HBM placement, routing density, power distribution, thermal behavior, assembly requirements, and manufacturing economics.</p> 1071 1072 1073 1074<figure class="wp-block-image"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-vs-silicon-interposer.jpg" alt="Comparison of a local EMIB bridge and a continuous silicon interposer"/></figure> 1075 1076 1077 1078<h2 class="wp-block-heading">EMIB vs CoWoS-L: How Do the Architectures Differ?</h2> 1079 1080 1081 1082<p>EMIB embeds localized silicon bridges directly inside the package substrate, while <a href="https://www.bestpcbs.com/blog/2026/09/cowos-l/">CoWoS-L</a> uses local silicon interconnect structures within a broader RDL-based interposer architecture. Both use localized silicon for dense connections, but the surrounding routing structures are different.</p> 1083 1084 1085 1086<div class="wp-block-table"> 1087<table> 1088<tbody> 1089<tr> 1090<td><strong>Feature</strong></td> 1091<td><strong>EMIB</strong></td> 1092<td><strong>CoWoS-L</strong></td> 1093</tr> 1094<tr> 1095<td>Local silicon structure</td> 1096<td>Embedded silicon bridge</td> 1097<td>Local Silicon Interconnect</td> 1098</tr> 1099<tr> 1100<td>Surrounding routing medium</td> 1101<td>Package substrate</td> 1102<td>RDL interposer</td> 1103</tr> 1104<tr> 1105<td>Fine-pitch routing</td> 1106<td>Localized</td> 1107<td>Localized</td> 1108</tr> 1109<tr> 1110<td>HBM integration</td> 1111<td>Supported</td> 1112<td>Supported</td> 1113</tr> 1114<tr> 1115<td>Package scaling</td> 1116<td>Multiple bridge regions</td> 1117<td>Larger RDL interposer with local silicon</td> 1118</tr> 1119<tr> 1120<td>Broader routing</td> 1121<td>Organic build-up layers</td> 1122<td>RDL structure</td> 1123</tr> 1124</tbody> 1125</table> 1126</div> 1127 1128 1129 1130<p>In an EMIB package, the organic substrate performs much of the broader routing around each silicon bridge. In CoWoS-L, the localized silicon structures are part of a larger redistribution-layer interposer system.</p> 1131 1132 1133 1134<p>A practical comparison should consider more than the presence of a bridge. Engineers also need to evaluate:</p> 1135 1136 1137 1138<ul class="wp-block-list"> 1139<li>die and HBM placement;</li> 1140 1141 1142 1143<li>routing density;</li> 1144 1145 1146 1147<li>package dimensions;</li> 1148 1149 1150 1151<li>power distribution;</li> 1152 1153 1154 1155<li>warpage;</li> 1156 1157 1158 1159<li>thermal behavior;</li> 1160 1161 1162 1163<li>assembly flow;</li> 1164 1165 1166 1167<li>yield;</li> 1168 1169 1170 1171<li>overall package cost.</li> 1172</ul> 1173 1174 1175 1176<p>These architectural differences become increasingly important as AI and HPC packages integrate more compute silicon and memory within the same package footprint.</p> 1177 1178 1179 1180<figure class="wp-block-image"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-vs-cowos-l.jpg" alt="EMIB substrate bridge compared with the distinct RDL and local silicon interconnect architecture of CoWoS-L"/></figure> 1181 1182 1183 1184<h2 class="wp-block-heading">EMIB, EMIB-M and EMIB-T: What Is the Difference?</h2> 1185 1186 1187 1188<p>EMIB, EMIB-M, and <a href="https://www.bestpcbs.com/blog/2026/09/emib-t-substrate/">EMIB-T</a> share the same localized silicon-bridge concept, but the newer variants add specific electrical functions. Standard EMIB focu
1188ses mainly on lateral routing, while EMIB-M and EMIB-T expand the role of the bridge.</p> 1189 1190 1191 1192<div class="wp-block-table"> 1193<table> 1194<tbody> 1195<tr> 1196<td><strong>Technology</strong></td> 1197<td><strong>Main Addition</strong></td> 1198<td><strong>Primary Function</strong></td> 1199</tr> 1200<tr> 1201<td>EMIB</td> 1202<td>Local silicon bridge</td> 1203<td>Fine-pitch lateral die-to-die routing</td> 1204</tr> 1205<tr> 1206<td>EMIB-M</td> 1207<td>Integrated MIM capacitance</td> 1208<td>Local decoupling and power support</td> 1209</tr> 1210<tr> 1211<td>EMIB-T</td> 1212<td>TSVs through the bridge</td> 1213<td>Vertical electrical and power paths</td> 1214</tr> 1215</tbody> 1216</table> 1217</div> 1218 1219 1220 1221<p>EMIB-M integrates metal-insulator-metal capacitance close to the dies, which can support local power delivery and decoupling. EMIB-T adds through-silicon vias, allowing selected electrical paths to move vertically through the bridge.</p> 1222 1223 1224 1225<p>The distinction is especially relevant for newer AI and HBM packages. As current demand increases, the bridge can evolve from a primarily signal-routing structure into a more active part of the package power-delivery architecture.</p> 1226 1227 1228 1229<figure class="wp-block-image"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-emib-m-emib-t.jpg" alt="Comparison of conventional EMIB routing, EMIB-M capacitors and EMIB-T bridge TSVs"/></figure> 1230 1231 1232 1233<h2 class="wp-block-heading">How Does EMIB Connect Chiplets, HBM and UCIe?</h2> 1234 1235 1236 1237<p>EMIB provides the physical high-density connection between neighboring chiplets or between logic and HBM. The silicon bridge carries the electrical signals, while standards such as UCIe define how compatible chiplets communicate at the interface level.</p> 1238 1239 1240 1241<p>Typical EMIB connections include:</p> 1242 1243 1244 1245<ul class="wp-block-list"> 1246<li>compute die to compute die;</li> 1247 1248 1249 1250<li>compute die to I/O die;</li> 1251 1252 1253 1254<li>compute die to HBM;</li> 1255 1256 1257 1258<li>accelerator to accelerator;</li> 1259 1260 1261 1262<li>UCIe-compatible chiplet links.</li> 1263</ul> 1264 1265 1266 1267<p>HBM is a strong use case because its wide interface benefits from short routing distances and high connection density. Chiplet interfaces have similar requirements when several dies need to exchange large volumes of data within the same package.</p> 1268 1269 1270 1271<p>UCIe and EMIB therefore address different layers of the connection. UCIe defines the die-to-die interface framework, while EMIB can provide the physical package interconnect that carries those signals between adjacent dies.</p> 1272 1273 1274 1275<h2 class="wp-block-heading">Where Is EMIB Used in AI and HPC Packaging?</h2> 1276 1277 1278 1279<p>EMIB is used in advanced packages where multiple high-performance dies, memory stacks, or specialized chiplets require dense local interconnections. These applications increasingly depend on package-level bandwidth as much as on transistor performance.</p> 1280 1281 1282 1283<p>Common application areas include:</p> 1284 1285 1286 1287<ul class="wp-block-list"> 1288<li>AI training accelerators;</li> 1289 1290 1291 1292<li>AI inference processors;</li> 1293 1294 1295 1296<li>HPC processors;</li> 1297 1298 1299 1300<li>data-center CPUs;</li> 1301 1302 1303 1304<li>FPGAs;</li> 1305 1306 1307 1308<li>multi-die GPUs and XPUs;</li> 1309 1310 1311 1312<li>chiplet-based compute platforms;</li> 1313 1314 1315 1316<li>logic-plus-HBM packages.</li> 1317</ul> 1318 1319 1320 1321<p>Heterogeneous integration also allows each die to use a manufacturing process suited to its function. Compute cores can use an advanced node, while I/O, analog, or supporting logic can remain on nodes better suited to cost, voltage, or interface requirements.</p> 1322 1323 1324 1325<p>This approach helps designers scale system performance without increasing every function inside one extremely large monolithic die.</p> 1326 1327 1328 1329<h2 class="wp-block-heading">Can EMIB Use a Glass-Core Substrate?</h2> 1330 1331 1332 1333<p>EMIB can potentially be integrated with glass-core substrate platforms as advanced packages move toward larger dimensions and tighter registration requirements. Conventional EMIB, however, should still be understood as an embedded silicon-bridge architecture rather than a technology defined by glass substrates.</p> 1334 1335 1336 1337<p>Glass-core substrates are being explored because they can offer useful properties for very large advanced packages:</p> 1338 1339 1340 1341<ul class="wp-block-list"> 1342<li>improved dimensional stability;</li> 1343 1344 1345 1346<li>lower warpage potential;
1346</li> 1347 1348 1349 1350<li>support for larger package formats;</li> 1351 1352 1353 1354<li>finer routing capability;</li> 1355 1356 1357 1358<li>stable electrical characteristics;</li> 1359 1360 1361 1362<li>support for dense vertical and lateral interconnects.</li> 1363</ul> 1364 1365 1366 1367<p>Glass also introduces manufacturing challenges, including via formation, metallization, substrate handling, bonding, and integration with organic build-up layers. These processes must meet the same reliability and production requirements expected from established package-substrate platforms.</p> 1368 1369 1370 1371<p>For future EMIB scaling, improved substrate stability could become increasingly valuable as packages integrate more silicon bridges, chiplets, and HBM stacks while maintaining tight alignment across a larger area.</p> 1372 1373 1374 1375<h2 class="wp-block-heading">EMIB FAQs</h2> 1376 1377 1378 1379<p><strong>1. What does EMIB stand for? </strong></p> 1380 1381 1382 1383<p>EMIB stands for Embedded Multi-die Interconnect Bridge. It uses small silicon bridges embedded inside a package substrate to create fine-pitch connections between neighboring dies.</p> 1384 1385 1386 1387<p><strong>2. Is EMIB a 2.5D packaging technology?</strong> </p> 1388 1389 1390 1391<p>Yes. EMIB is generally classified as a 2.5D heterogeneous integration technology because multiple dies are placed side by side and connected through localized high-density silicon interconnects.</p> 1392 1393 1394 1395<p><strong>3. Does EMIB use TSVs? </strong></p> 1396 1397 1398 1399<p>Conventional EMIB bridges do not require TSVs for their primary lateral die-to-die connection. EMIB-T is the variant that adds TSVs through the bridge for vertical electrical and power paths.</p> 1400 1401 1402 1403<p><strong>4. What is an EMIB substrate? </strong></p> 1404 1405 1406 1407<p>An EMIB substrate is a package substrate containing embedded silicon bridges beneath selected die interfaces. The bridges handle fine-pitch routing, while the surrounding substrate carries broader signals, power, and ground.</p> 1408 1409 1410 1411<p><strong>5. What is the difference between EMIB and CoWoS? </strong></p> 1412 1413 1414 1415<p>EMIB places localized silicon bridges directly inside the package substrate. CoWoS is an interposer-based packaging family, while CoWoS-L combines localized silicon interconnects with a broader RDL interposer structure.</p> 1416 1417 1418 1419<p><strong>6. What is the difference between EMIB and EMIB-T? </strong></p> 1420 1421 1422 1423<p>Standard EMIB mainly provides lateral die-to-die routing through an embedded silicon bridge. EMIB-T adds TSVs through that bridge, creating vertical electrical paths that can support more demanding power-delivery requirements.</p> 1424 1425 </div> 1426 1427 1428 1429 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/emib/" rel="tag">EMIB</a>, <a href="https://www.bestpcbs.com/blog/tag/emib-process-flow/" rel="tag">emib process flow</a>, <a href="https://www.bestpcbs.com/blog/tag/emib-substrate/" rel="tag">emib substrate</a>, <a href="https://www.bestpcbs.com/blog/tag/emib-technology/" rel="tag">emib technology</a>, <a href="https://www.bestpcbs.com/blog/tag/emib-vs-cowos/" rel="tag">emib vs cowos</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/pcb-design/" rel="category tag">PCB Design</a>, <a href="https://www.bestpcbs.com/blog/category/pcb-technology/" rel="category tag">PCB Technology</a> | <a href="https://www.bestpcbs.com/blog/2026/10/emib/#respond">No Comments »</a></p> 1430 1431 </div> 1432 1433 1434 1435 1436 1437 1438 <div class="post-36708 post type-post status-publish format-standard hentry category-best-pcb category-bestpcb category-pcb-design tag-pcie-differential-pair-routing tag-pcie-length-matching tag-pcie-routing-guidelines" id="post-36708"> 1439 1440 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/10/pcie-routing-guidelines/" rel="bookmark" title="Permanent Link to PCIe Routing Guidelines for PCB Design: Impedance, Length Matching, Vias, and Stackup">PCIe Routing Guidelines for PCB Design: Impedance, Length Matching, Vias, and Stackup</a></h1> 1441 1442 <small>October 2nd, 2026 <!-- by Jessica, Jessica --></small> 1443 1444 1445 1446 <div class="entry"> 1447 1448 <div class="yzp-no-index"></div> 1449<p><strong><a href="https://www.bestpcbs.com/blog/2026/09/pcie-routing-guidelines/" title="">PCIe routing guidelines</a> help you control differential impedance, P/N matching, trace spacing, via transitions, return paths, and PCB stackup so the link can maintain reliable signal integrity at the target data rate.</strong> These routing decisions become more sensitive as PCIe speed increases, especially when the channel includes long traces, connectors, multiple layer changes, or thick PCBs.</p> 1450 1451 1452 1453<p>This guide focuses on the <strong><a href="https://www.bestpcbs.com/blog/2026/09/pcie-routing-guidelines/" title="">PCIe routing guidelines</a> you can apply directly during PCB layout</strong>, including differential impedance, pair routing, spacing, length matching, vias, AC coupling, low-loss materials, backdrilling, and the checks to complete before releasing the PCB for fabrication.</p> 1454 1455 1456 1457<figure class="wp-block-image size-full is-resized"><a href="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines.jpg"><img fetchpriority="high" decoding="async" width="800" height="500" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines.jpg" alt="PCIe Routing Guidelines, https://www.bestpcbs.com/blog/2026/10/pcie-routing-guidelines/" class="wp-image-36738" style="aspect-ratio:3/2;object-fit:cover;width:700px" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines.jpg 800w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-300x188.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-768x480.jpg 768w" sizes="(max-width: 800px) 100v
1457w, 800px" /></a></figure> 1458 1459 1460 1461<h2 class="wp-block-heading">What Are the Basic PCIe Routing Guidelines?</h2> 1462 1463 1464 1465<p>Before routing the first lane, confirm the <strong>PCIe generation, transmitter and receiver, channel topology, impedance target, and final PCB stackup</strong>. These decisions determine most of the routing constraints that follow.</p> 1466 1467 1468 1469<p>Use these <strong>PCIe routing guidelines</strong> as the starting point:</p> 1470 1471 1472 1473<ul class="wp-block-list"> 1474<li><strong>Define the stackup before setting trace width and P/N gap.</strong> Both depend on dielectric thickness, finished copper, and reference-plane distance.</li> 1475 1476 1477 1478<li><strong>Use the impedance specified for the actual PCIe interface.</strong> Do not assume that every controller, FPGA, SoC, or connector uses the same value.</li> 1479 1480 1481 1482<li><strong>Route P and N together.</strong> Keep both conductors on the same layer with similar bends, neck-downs, pads, and via transitions.</li> 1483 1484 1485 1486<li><strong>Match P to N before matching separate lanes.</strong> Intra-pair skew and lane-to-lane skew are different constraints.</li> 1487 1488 1489 1490<li><strong>Keep a continuous reference plane beneath the route.</strong> Avoid plane splits, slots, and large voids.</li> 1491 1492 1493 1494<li><strong>Separate neighboring lanes enough to control crosstalk.</strong> P/N gap and pair-to-pair spacing solve different problems.</li> 1495 1496 1497 1498<li><strong>Minimize layer changes.</strong> Every transition introduces vias and can leave an unused via stub.</li> 1499 1500 1501 1502<li><strong>Keep P/N via structures symmetrical.</strong> Both conductors should see similar drills, pads, antipads, and layer spans.</li> 1503 1504 1505 1506<li><strong>Route AC coupling capacitors symmetrically.</strong> Keep both paths short and balanced through the component footprints.</li> 1507 1508 1509 1510<li><strong>Use low-loss material or backdrilling only when the route justifies it.</strong> Neither should be added automatically because the interface is PCIe Gen 4 or Gen 5.</li> 1511</ul> 1512 1513 1514 1515<p>These rules cover the layout decisions that have the greatest direct impact on PCIe routing.</p> 1516 1517 1518 1519<h2 class="wp-block-heading">What Differential Impedance Should PCIe Traces Use?</h2> 1520 1521 1522 1523<p><strong>Use the differential impedance specified by the controller, FPGA, SoC, connector, or platform you are designing around.</strong> An <strong>85 Ω differential target is common in many PCIe implementations</strong>, while some chip-to-chip links may use 100 Ω. The correct value is the one defined for the actual interface.</p> 1524 1525 1526 1527<p>Once the target is known, set the geometry from the real PCB construction:</p> 1528 1529 1530 1531<ol class="wp-block-list"> 1532<li><strong>Choose the routing layer and reference plane.</strong></li> 1533 1534 1535 1536<li><strong>Use the actual dielectric thickness and finished copper thickness.</strong></li> 1537 1538 1539 1540<li><strong>Solve trace width and P/N gap together.</strong></li> 1541 1542 1543 1544<li><strong>Check whether that geometry can pass through the BGA escape and connector area.</strong></li> 1545 1546 1547 1548<li><strong>Recalculate the pair if the stackup changes.</strong></li> 1549</ol> 1550 1551 1552 1553<p>One of the most important <strong>PCIe routing guidelines</strong> is to derive the width and gap from the final stackup rather than copy a geometry from another board. A 4 mil trace with a 6 mil gap can produce a different impedance when dielectric thickness, copper thickness, or reference-plane distance changes.</p> 1554 1555 1556 1557<p>The P/N gap should also not be adjusted independently just to make routing easier. <strong>Trace width, pair gap, copper thickness, dielectric thickness, and reference-plane distance form one transmission-line structure.</strong></p> 1558 1559 1560 1561<p>If the nominal geometry cannot pass through a dense BGA breakout, use a <strong>short, symmetrical neck-down</strong>. Keep both conductors similar and return to the normal controlled-impedance geometry as soon as the breakout allows.</p> 1562 1563 1564 1565<figure class="wp-block-image size-large is-resized"><a href="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-2.png"><img decoding="async" width="1024" height="683" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-2-1024x683.png" alt="PCIe Routing Guidelines, https://www.bestpcbs.com/blog/2026/10/pcie-routing-guidelines/" class="wp-image-36740" style="aspect-ratio:3/2;object-fit:cover;width:700px" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-2-1024x683.png 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-2-300x200.png 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-2-768x512.png 768w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-2.png 1536w" sizes="(max-width: 1024px) 100vw, 1024px" /></a></figure> 1566 1567 1568 1569<h2 class="wp-block-heading">Which PCIe Routing Guidelines Apply to Differential Pair Routing?</h2> 1570 1571 1572 1573<p><strong>Route each PCIe P/N pair as one electrical structure and keep its geometry as consistent as practical from transmitter to receiver.</strong> The long straight portion of a route is usually straightforward; BGA breakouts, capacitor pads, connectors, bends, and vias are where asymmetry is more likely to appear.</p> 1574 1575 1576 1577<p>For the main route:</p> 1578 1579 1580 1581<ul class="wp-block-list"> 1582<li><strong>Keep P and N on the same layer.</strong></li> 1583 1584 1585 1586<li><strong>Maintain the calculated trace width and pair gap.</strong></li> 1587 1588 1589 1590<li><strong>Use similar bends on both conductors.</strong></li> 1591 1592 1593 1594<li><strong>Keep pad entry and exit geometry balanced.</strong></li> 1595 1596 1597 1598<li><strong>Keep BGA neck-down sections short.</strong></li> 1599 1600 1601 1602<li><strong>Avoid branches, unused trace extensions, and conventional test-point stubs.</strong></li> 1603 1604 1605 1606<li><strong>Do not separate P and N for long distances.</strong></li> 1607 1608 1609 1610<li><strong>Avoid routing one conductor around an obstacle while the other remains straight.</strong></li> 1611 1612 1613 1614<li><strong>Minimize unnecessary layer changes.</strong></li> 1615</ul> 1616 1617 1618 1619<p>The objective is not visual symmetry for its own sake. <strong>P and N should experience nearly the same electrical environment.</strong> A short, balanced deviation is usually better than forcing one conductor into a very different path.</p> 1620 1621 1622 1623<p>Do not make the P/N gap smaller simply because tighter coupling appears safer. The correct gap comes from the impedance solution. An unnecessarily tight pair can make BGA escape more difficult and increase sensitivity to fabrication variation.</p> 1624 1625 1626 1627<h2 class="wp-block-heading">How Much Spacing Should PCIe Traces Have?</h2> 1628 1629 1630 1631<p><strong>The P/N gap inside one differential pair and the spacing between separate PCIe pairs are not the same rule.</strong></p> 1632 1633 1634 1635<p>The <strong>P/N gap</strong> is part of the differential-impedance geometry. Once the stackup and impedance target are fixed, keep that gap stable through the main route unless a short constrained region requires a controlled change.</p> 1636 1637 1638 1639<p>The spacing between different PCIe pairs is mainly used to limit crosstalk. Increase clearance when:</p> 1640 1641 1642 1643<ul class="wp-block-list"> 1644<li>
1644Two lanes run parallel for a long distance.</li> 1645 1646 1647 1648<li>A PCIe lane runs beside a reference clock.</li> 1649 1650 1651 1652<li>DDR, USB, Ethernet, or another high-speed interface is nearby.</li> 1653 1654 1655 1656<li>Switching power circuitry is close to the route.</li> 1657 1658 1659 1660<li>Several high-speed pairs share a narrow routing corridor.</li> 1661</ul> 1662 1663 1664 1665<p>For spacing, <strong>PCIe routing guidelines</strong> should distinguish between the geometry that sets impedance and the clearance used to reduce coupling. Parallel length matters as much as physical separation: two pairs close together for a few millimeters do not present the same risk as two pairs running side by side across most of the PCB.</p> 1666 1667 1668 1669<p>If routing space is limited, <strong>reduce the distance over which two lanes run in parallel before squeezing the clearance along the entire route</strong>. Moving one pair earlier, changing routing direction, or shortening the shared corridor can be more useful than applying a tighter global spacing rule.</p> 1670 1671 1672 1673<p>Rules such as <strong>3W or 5W</strong> can be useful as starting heuristics, but they should not be treated as universal PCIe limits. The final spacing should reflect the actual stackup, reference-plane distance, parallel length, and nearby aggressors.</p> 1674 1675 1676 1677<h2 class="wp-block-heading">How Much Length Matching Does PCIe Need?</h2> 1678 1679 1680 1681<p><strong>Match P to N within each lane first. Do not automatically tune every PCIe lane to exactly the same physical length.</strong></p> 1682 1683 1684 1685<p>Three different constraints are often confused:</p> 1686 1687 1688 1689<ul class="wp-block-list"> 1690<li><strong>Intra-pair skew:</strong> the difference between P and N inside one differential pair.</li> 1691 1692 1693 1694<li><strong>Inter-lane skew:</strong> the delay difference between separate PCIe lanes.</li> 1695 1696 1697 1698<li><strong>Channel reach:</strong> the complete electrical path from transmitter to receiver.</li> 1699</ul> 1700 1701 1702 1703<p>Practical <strong>PCIe routing guidelines</strong> prioritize intra-pair P/N matching before unnecessary lane-to-lane tuning. Excessive P/N mismatch reduces differential symmetry, so use the skew limit specified by the selected controller or platform rather than copying a generic value from another design.</p> 1704 1705 1706 1707<p>PCIe receivers can deskew multiple lanes, which means an x4, x8, or x16 link does not automatically require every pair to have identical copper length. If the platform specifies a lane-to-lane limit, handle it separately from P/N matching.</p> 1708 1709 1710 1711<p>When tuning is required:</p> 1712 1713 1714 1715<ul class="wp-block-list"> 1716<li><strong>Correct the mismatch close to where it occurs when practical.</strong></li> 1717 1718 1719 1720<li><strong>Use only as much serpentine routing as necessary.</strong></li> 1721 1722 1723 1724<li><strong>Keep neighboring meander segments far enough apart to limit self-coupling.</strong></li> 1725 1726 1727 1728<li><strong>Avoid dense accordion-style tuning.</strong></li> 1729 1730 1731 1732<li><strong>Do not create a crosstalk problem just to correct a small length difference.</strong></li> 1733</ul> 1734 1735 1736 1737<p>TX and RX also do not need to have the same physical length simply because they belong to the same PCIe interface. Each direction should satisfy its own routing constraints.</p> 1738 1739 1740 1741<h2 class="wp-block-heading">What PCIe Routing Guidelines Apply to Vias and Layer Changes?</h2> 1742 1743 1744 1745<p><strong>Use as few layer changes as practical and treat each transition as a combined signal-and-return structure.</strong> A PCIe via is not automatically a problem; the concern is whether the transition keeps P/N geometry balanced, preserves the return path, and leaves an acceptable via stub.</p> 1746 1747 1748 1749<p>When changing layers, check:</p> 1750 1751 1752 1753<ul class="wp-block-list"> 1754<li><strong>P/N via symmetry:</strong> both signal vias should use similar drills, pads, and layer spans.</li> 1755 1756 1757 1758<li><strong>Trace entry and exit:</strong> keep the approach to both vias balanced.</li> 1759 1760 1761 1762<li><strong>Antipad geometry:</strong> avoid noticeably different plane openings around P and N.</li> 1763 1764 1765 1766<li><strong>Ground stitching:</strong> provide a short return path between ground reference planes.</li> 1767 1768 1769 1770<li><strong>Unused barrel:</strong>
1770 identify how much plated via remains above or below the signal exit.</li> 1771</ul> 1772 1773 1774 1775<p>A common problem occurs when a signal enters a through via from the top layer and exits on an upper inner layer of a thick PCB. <strong>Most of the barrel below the signal layer remains unused</strong>, so the resulting stub can be much longer than it would be if the signal exited near the bottom of the board.</p> 1776 1777 1778 1779<p>Before specifying backdrilling, check whether you can reduce the stub by changing the routing layer, shortening the via span, or using a blind or buried via. If those options are not practical and the remaining barrel affects the channel, backdrilling becomes a reasonable option.</p> 1780 1781 1782 1783<p>The reference path must remain continuous as well. Do not cross a plane split simply because P and N cross it together. When moving between two ground-referenced layers, place ground stitching vias close to the signal transition so the return current does not have to take a long detour.</p> 1784 1785 1786 1787<h2 class="wp-block-heading">Where Should PCIe AC Coupling Capacitors Be Placed?</h2> 1788 1789 1790 1791<p><strong>Place PCIe AC coupling capacitors according to the selected device or platform guidance, then route through the footprints as part of the differential pair.</strong> The capacitor area should not become a large geometry change in an otherwise controlled channel.</p> 1792 1793 1794 1795<p>Keep the layout simple:</p> 1796 1797 1798 1799<ul class="wp-block-list"> 1800<li><strong>Use the required capacitance and package.</strong></li> 1801 1802 1803 1804<li><strong>Use matching components on P and N.</strong></li> 1805 1806 1807 1808<li><strong>Align both capacitor footprints.</strong></li> 1809 1810 1811 1812<li><strong>Keep entry and exit routing symmetrical.</strong></li> 1813 1814 1815 1816<li><strong>Keep fan-in and fan-out short.</strong></li> 1817 1818 1819 1820<li><strong>Avoid long neck-down sections.</strong></li> 1821 1822 1823 1824<li><strong>Avoid unused pad extensions or test branches.</strong></li> 1825 1826 1827 1828<li><strong>Check whether another board or module already includes the required AC coupling.</strong></li> 1829</ul> 1830 1831 1832 1833<p>The preferred transition is:</p> 1834 1835 1836 1837<p><strong>controlled pair â short capacitor transition â controlled pair</strong></p> 1838 1839 1840 1841<p>If one conductor travels through a different pad approach or noticeably longer route than the other, the capacitor region can introduce unnecessary asymmetry.</p> 1842 1843 1844 1845<p>Also confirm the TX direction before placement. PCIe TX and RX are separate unidirectional channels, so the AC coupling capacitor groups for each direction may be physically located near different devices.</p> 1846 1847 1848 1849<figure class="wp-block-image size-large is-resized"><a href="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-3-1.png"><img decoding="async" width="1024" height="683" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-3-1-1024x683.png" alt="PCIe Routing Guidelines, https://www.bestpcbs.com/blog/2026/10/pcie-routing-guidelines/" class="wp-image-36744" style="aspect-ratio:3/2;object-fit:cover;width:700px" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-3-1-1024x683.png 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-3-1-300x200.png 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-3-1-768x512.png 768w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/10/PCIe-Routing-Guidelines-3-1.png 1536w" sizes="(max-width: 1024px) 100vw, 1024px" /></a></figure> 1850 1851 1852 1853<h2 class="wp-block-heading">When Do PCIe Routes Need Low-Loss Material or Backdrilling?</h2> 1854 1855 1856 1857<p><strong>Use low-loss material when distributed channel loss is the problem; use backdrilling when a via stub is the problem.</strong> These two decisions should be made from the actual route rather than the PCIe generation alone.</p> 1858 1859 1860 1861<figure class="wp-block-table"><table class="has-fixed-layout"><thead><tr><th><strong>Condition</strong></th><th><strong>What to Check</strong></th></tr></thead><tbody><tr><td>Long PCB route</td><td>Total insertion loss</td></tr><tr><td>Multiple connectors</td><td>Combined connector and channel loss</td></tr><tr><td>High-loss laminate</td><td>Whether dielectric loss consumes too much margin</td></tr><tr><td>Rough copper</td><td>Conductor-loss contribution</td></tr><tr><td>Thick PCB with short via span</td><td>Remaining via stub</td></tr><tr><td>Long unused via barrel</td><td>Whether backdrilling is warranted</td></tr><tr><td>Short onboard route</td><td>Standard or improved FR-4 may be sufficient</td></tr><tr><td>Limited Gen 5 margin</td><td>Review both material loss and via transitions</td></tr></tbody></table></figure> 1862 1863 1864 1865<p>Low-loss material becomes more useful when the route is long, several connectors are present, or dielectric and conductor losses consume too much margin. <strong>A short onboard route with few transitions may not justify an expensive low-loss laminate simply because it runs PCIe Gen 4 or Gen 5.</strong></p> 1866 1867 1868 1869<p>Backdrilling addresses a different issue. If a through via leaves a long unused barrel, that stub can create a significant discontinuity. The risk is greater on thicker PCBs where the signal exits close to one side of the board.</p> 1870 1871 1872 1873<p>The distinction is straightforward:</p> 1874 1875 1876 1877<p><strong>Low-loss laminate reduces loss along the route. Backdrilling reduces the discontinuity caused by unused via barrel.</strong></p> 1878 1879 1880 1881<p>One does not replace the other.</p> 1882 1883 1884 1885<h2 class="wp-block-heading">Which PCIe Routing Guidelines Should You Check Before PCB Release?</h2> 1886 1887 1888 1889<p>
1889Before generating final fabrication data, use these <strong>PCIe routing guidelines</strong> as a final check of the actual routed channel rather than relying only on the CAD rule report.</p> 1890 1891 1892 1893<p>Confirm the following:</p> 1894 1895 1896 1897<ul class="wp-block-list"> 1898<li><strong>Is the differential impedance based on the final PCB stackup?</strong></li> 1899 1900 1901 1902<li><strong>Do P and N stay on the same layer through the main route?</strong></li> 1903 1904 1905 1906<li><strong>Are BGA neck-downs short and symmetrical?</strong></li> 1907 1908 1909 1910<li><strong>Does P/N skew meet the applicable requirement?</strong></li> 1911 1912 1913 1914<li><strong>Have lane-to-lane limits been checked separately where required?</strong></li> 1915 1916 1917 1918<li><strong>Are long parallel PCIe lanes sufficiently separated?</strong></li> 1919 1920 1921 1922<li><strong>Are clocks and other strong aggressors kept away from the route?</strong></li> 1923 1924 1925 1926<li><strong>Does every route section have a continuous reference plane?</strong></li> 1927 1928 1929 1930<li><strong>Do layer transitions include an appropriate return path?</strong></li> 1931 1932 1933 1934<li><strong>Are P/N signal vias symmetrical?</strong></li> 1935 1936 1937 1938<li><strong>Have long unused via stubs been identified?</strong></li> 1939 1940 1941 1942<li><strong>Are AC coupling capacitors routed symmetrically?</strong></li> 1943 1944 1945 1946<li><strong>Does the selected PCB material provide enough loss margin?</strong></li> 1947 1948 1949 1950<li><strong>Are required backdrill locations clearly defined?</strong></li> 1951 1952 1953 1954<li><strong>Has the stackup remained unchanged since the impedance geometry was calculated?</strong></li> 1955</ul> 1956 1957 1958 1959<p>If several of these items are difficult to confirm, review the routing before release. The final layout should keep <strong>impedance, P/N symmetry, spacing, length matching, vias, and return paths consistent across the same PCIe channel</strong>, rather than simply passing separate CAD checks.</p> 1960 1961 1962 1963<h2 class="wp-block-heading">FAQs About PCIe Routing Guidelines</h2> 1964 1965 1966 1967<p><strong>Q1: Can PCIe P and N be swapped?</strong><br><strong>A1: Many PCIe implementations support polarity inversion within a differential pair.</strong> Confirm that the selected controller and endpoint support it before using P/N swapping to simplify routing.</p> 1968 1969 1970 1971<p><strong>Q2: Can PCIe lanes be reordered during BGA breakout?</strong><br><strong>A2: Only when the selected devices support lane reversal or lane mapping.</strong> Lane reordering is different from swapping P and N within one differential pair.</p> 1972 1973 1974 1975<p><strong>Q3: Can PCIe traces use 90-degree bends?</strong><br><strong>A3: Avoid abrupt geometry changes where practical.</strong> Smooth or 45-degree routing is usually easier to keep symmetrical, but maintaining consistent P/N geometry matters more than the visual bend angle alone.</p> 1976 1977 1978 1979<p><strong>Q4: Can PCIe traces run on an outer PCB layer?</strong><br><strong>A4: Yes, as long as the outer-layer geometry is designed for the required impedance.</strong> Include solder mask and the actual reference-plane distance in the impedance calculation.</p> 1980 1981 1982 1983<p><strong>Q5: Does solder mask affect PCIe impedance?</strong><br><strong>A5: Yes, particularly for microstrip routing.</strong> Solder mask changes the dielectric environment around the trace and should be included in the impedance model.</p> 1984 1985 1986 1987<p><strong>Q6: Can test points be added to PCIe traces?</strong><br><strong>A6: Avoid conventional branched test points because they create stubs.</strong> If measurement access is required, use a probing structure suitable for the required bandwidth.</p> 1988 1989 1990 1991<p><strong>Q7: Can PCIe traces pass through a dense BGA breakout?</strong><br><strong>A7: Yes.</strong> Use a short, symmetrical neck-down where necessary and return to the normal controlled-impedance geometry after leaving the escape region.</p> 1992 1993 1994 1995<p><strong>Q8: Can PCIe and USB share the same routing layer?</strong><br><strong>A8: Yes, if the interfaces have enough separation and do not run parallel for unnecessarily long distances.</strong> Each interface should still follow its own impedance and routing constraints.</p> 1996 1997 1998 1999<p><strong>Q9: Does fiber weave affect PCIe routing?</strong><br><strong>A9: It can become relevant on longer, higher-speed routes because P and N may travel through different glass and resin distributions.</strong> If skew margin is tight, review the laminate construction and routing direction.</p> 2000 2001 2002 2003<p><strong>Q10: Should ground copper be poured next to PCIe pairs?</strong><br><strong>A10: Only when it is intentionally included in the impedance geometry.</strong> Nearby copper with inconsistent clearance can change both impedance and coupling along the route.</p> 2004 2005 2006 2007<p>Applying these <strong>
2007PCIe routing guidelines</strong> consistently helps keep impedance, P/N symmetry, spacing, vias, and reference paths under control before the board reaches fabrication. Before release, verify that the <strong>final stackup, controlled-impedance geometry, P/N matching, reference planes, via structure, and material still match the assumptions used during layout</strong>.</p> 2008 2009 2010 2011<p>If you want to review the manufacturability of a completed PCIe PCB before production, send your <strong>Gerber or ODB++ files, proposed stackup, impedance requirements, quantity, and delivery target</strong> to <strong><a>[email protected]</a></strong>.</p> 2012 2013 </div> 2014 2015 2016 2017 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/pcie-differential-pair-routing/" rel="tag">PCIe Differential Pair Routing</a>, <a href="https://www.bestpcbs.com/blog/tag/pcie-length-matching/" rel="tag">PCIe Length Matching</a>, <a href="https://www.bestpcbs.com/blog/tag/pcie-routing-guidelines/" rel="tag">PCIe Routing Guidelines</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/bestpcb/" rel="category tag">bestpcb</a>, <a href="https://www.bestpcbs.com/blog/category/pcb-design/" rel="category tag">PCB Design</a> | <a href="https://www.bestpcbs.com/blog/2026/10/pcie-routing-guidelines/#respond">No Comments »</a></p> 2018 2019 </div> 2020 2021 2022 2023 2024 2025 2026 <div class="post-36699 post type-post status-publish format-standard hentry category-best-pcb category-bestpcb category-pcb-assembly-pcba tag-single-sided-pcb-assembly tag-smt-assembly tag-through-hole-assembly-2" id="post-36699"> 2027 2028 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/10/single-sided-pcb-assembly/" rel="bookmark" title="Permanent Link to Single Sided PCB Assembly for Cost-Efficient Production">Single Sided PCB Assembly for Cost-Efficient Production</a></h1> 2029 2030 <small>October 2nd, 2026 <!-- by zeng, liuyan --></small> 2031 2032 2033 2034 <div class="entry"> 2035 2036 <div class="yzp-no-index"></div> 2037<p><a href="https://www.bestpcbs.com/blog/2026/09/single-sided-pcb-assembly/">Single sided PCB assembly</a> can reduce production complexity when every component fits on one assembly side and the soldering process remains straightforward. The real advantage is not simply having fewer populated surfaces. It is avoiding unnecessary second-side placement, extra board handling, and additional process steps while still meeting the productâs electrical, mechanical, thermal, and inspection requirements.</p> 2038<p>EBest Circuit manufactures bare PCBs and assembles customer-designed boards with SMT, through-hole, or mixed component populations. By reviewing the approved PCB data, BOM, component packages, polarity information, and test requirements together, we help customers move from prototype quantities to repeat production with fewer avoidable process changes. For a quotation or DFM review, contact <strong>[email protected]</strong>.</p> 2039<figure class="wp-block-image size-full"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/single-sided-pcb-assembly-1.jpg" alt="single sided PCB assembly" /><figcaption class="wp-element-caption">A single-sided PCBA keeps all component bodies accessible on one populated surface.</figcaption></figure> 2040<h2>What Is Single Sided PCB Assembly?</h2> 2041<p>Single sided PCB assembly means that all mounted components are placed on one side of the finished circuit board. This describes the component population, not necessarily the number of copper layers inside the PCB. A board can have one copper layer and components on one side, but a multilayer PCB can also use single-sided assembly when all packages are mounted on the same surface.</p> 2042<p><strong><span style="color:#0070c0">That distinction matters because âsingle sidedâ can refer to three different features:</span></strong></p> 2043<ul> 2044<li><strong>A single sided PCB</strong> has one conductive copper layer.</li> 2045<li><strong>Single sided assembly</strong> places all components on one side of the board.</li> 2046<li><strong>Single-pass soldering</strong> describes a production route, but it does not automatically define the boardâs copper-layer count or component layout.</li> 2047</ul> 2048<p>
2048Traditional single-layer boards often combine through-hole parts inserted from the component side with leads soldered on the copper side. An SMT design usually places both pads and components on the copper-patterned surface. Mixed technology can combine SMT and through-hole parts on one populated side, although the solder joints may be formed through different processes.</p> 2049<p>The practical benefit appears when the circuit is simple enough to remain accessible on one side. Fewer placement surfaces can simplify tooling, handling, visual inspection, repair, and process control. Once jumpers, awkward package orientations, thermal crowding, or excessive board area are needed to preserve that restriction, the single-sided format may no longer be the lower-cost solution.</p> 2050<h2>How Are SMT and Through-Hole Components Placed on a Single Sided PCB?</h2> 2051<p>SMT and through-hole components can share a single sided PCB, but their mounting and soldering paths are different. Surface-mount packages sit directly on pads. Through-hole parts pass through drilled holes, and their leads are soldered on the opposite surface. The placement plan must therefore consider component access, lead direction, solder contact, and the order of each operation.</p> 2052<p><strong>For SMT-only assembly:</strong> <a href="https://www.bestpcbs.com/blog/2026/09/paste-volume-variation-pcb/">solder paste</a> is printed onto the pads, components are placed on the same surface, and the board passes through reflow. This is efficient for compact resistors, capacitors, ICs, and other packages that are suitable for automated placement.</p> 2053<p><strong>For through-hole assembly:</strong> parts are inserted from the component side and soldered from the reverse side by wave soldering, <a href="https://www.bestpcbs.com/blog/2026/09/selective-soldering-in-pcb-assembly/">selective soldering</a>, or a controlled manual process. Connectors, transformers, relays, and mechanically loaded parts often use this method when their package or retention requirements make through-hole mounting appropriate.</p> 2054<p><strong>For mixed assembly:</strong> SMT parts are usually placed and reflowed first. Through-hole parts are then inserted and soldered using a process compatible with the component bodies, spacing, and exposed SMT features. Pallets or selective soldering may be required when previously mounted parts must be protected from the solder wave.</p> 2055<p>Keeping all components on one side can make markings easier to read and service access more direct. However, the layout still needs adequate spacing around connectors, tall parts, polarized packages, test points, and soldering areas. A one-sided population only creates value if those features can be assembled without excessive manual correction or special handling.</p> 2056<h2>How Does Single Sided PCB Assembly Move Through Production?</h2> 2057<p>Single sided PCB assembly moves through production by matching the released board data and BOM to a controlled SMT, through-hole, or mixed-assembly route. A typical build follows this sequence:</p> 2058<figure class="wp-block-image size-full"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/single-sided-pcb-assembly-2.jpg" alt="single sided PCB assembly" /><figcaption class="wp-element-caption">A controlled process route can combine SMT and through-hole components on one assembly side.</figcaption></figure> 2059<ol> 2060<li><strong>Data and BOM review:</strong> Gerber or ODB++ data, drill files, drawings, centroid data, BOM details, component orientations, and revision identifiers are checked for agreement.</li> 2061<li><strong>Bare-board fabrication and inspection:</strong> the PCB is built to the approved stackup, copper, solder-mask, surface-finish, outline, and hole requirements before assembly begins.</li> 2062<li><strong>Material preparation:</strong> component identity, package, value, quantity, moisture sensitivity, polarity, and approved substitutions are controlled against the released BOM.</li> 2063<li><strong>SMT processing where required:</strong> solder paste is printed, paste deposition is checked, components are placed, and the board is reflowed under an established thermal profile.</li> 2064<li><strong>Through-hole processing where required:</strong> leads are inserted, formed when permitted, and soldered by the selected wave, selective, or manual method.</li> 2065<li><strong>Cleaning, inspection, and testing:</strong> residues are managed according to the process specification, solder joints and component placement are inspected, and the agreed electrical tests are completed.</li> 2066</ol> 2067<p>This route may be shorter than a two-sided assembly because the board does not require a second stencil print and placement cycle. It may al
2067so avoid the support, adhesive, or reflow considerations created by components on the underside. The actual saving depends on the component mix: a board dominated by manual through-hole work can still require substantial labor even though every part is on one side.</p> 2068<p>Stable repeat production depends on preserving the approved footprint geometry, solder volumes, component orientations, and process sequence. When a prototype uses hand-soldered substitutions or temporary jumpers, those exceptions should be resolved before the same board is treated as a production-ready single-sided assembly.</p> 2069<h2>What Determines Single Sided PCB Assembly Cost?</h2> 2070<p>Single sided <a href="https://www.bestpcbs.com/blog/2026/08/pcb-assembly-cost/">PCB assembly cost</a> is determined by the complete production route, not by component-side count alone. A one-sided population often costs less when it removes a second placement cycle, reduces fixtures and handling, and supports efficient panel processing. Those savings can disappear when the layout demands intensive manual insertion, unusual masking, selective soldering, rework, or a larger PCB.</p> 2071<p><strong><span style="color:#0070c0">The strongest cost drivers are:</span></strong></p> 2072<ul> 2073<li><strong>Component count and package mix:</strong> automated SMT placement is usually more scalable than repeated manual insertion, lead forming, or hand soldering.</li> 2074<li><strong>Board size and panel utilization:</strong> spreading a circuit over a larger one-sided board can reduce the number of units per panel and increase bare-board material cost.</li> 2075<li><strong>Assembly sequence:</strong> mixed SMT and through-hole builds require more operations than SMT-only boards, even when all components occupy one side.</li> 2076<li><strong>Tooling and soldering access:</strong> wave pallets, selective-solder fixtures, masking, or restricted nozzle access add setup and process time.</li> 2077<li><strong>Inspection and test coverage:</strong> AOI, X-ray where applicable, in-circuit testing, functional testing, programming, and custom fixtures affect non-recurring and per-unit cost.</li> 2078<li><strong>Volume and change frequency:</strong> prototypes absorb setup over few units, while stable repeat orders can distribute programming, stencil, tooling, and process-preparation costs more efficiently.</li> 2079</ul> 2080<p>The lowest quoted board price is therefore not always the lowest finished PCBA cost. If a single-sided constraint increases board area, jumper count, hand work, or defect opportunities, a compact double-sided layout may produce a better total cost. Cost comparison should use the same quantity, test scope, sourcing responsibility, quality requirements, and delivery assumptions so that the two assembly options are evaluated on equal terms.</p> 2081<h2>How Does Single Sided PCB Assembly Compare With Double Sided PCB Assembly?</h2> 2082<p>Single sided PCB assembly usually offers a simpler production path, while double sided PCB assembly provides more placement area and routing freedom. The better option depends on whether the second populated surface removes more cost and risk than it adds.</p> 2083<figure class="wp-block-table"> 2084<table> 2085<thead> 2086<tr> 2087<th>Production factor</th> 2088<th>Single sided assembly</th> 2089<th>Double sided assembly</th> 2090</tr> 2091</thead> 2092<tbody> 2093<tr> 2094<td>Component placement</td> 2095<td>All components occupy one surface</td> 2096<td>Components are placed on both surfaces</td> 2097</tr> 2098<tr> 2099<td>Typical process flow</td> 2100<td>One SMT placement side, with optional THT operations</td> 2101<td>Two placement sequences may be required</td> 2102</tr> 2103<tr> 2104<td>Board area</td> 2105<td>May need more area for the same component count</td> 2106<td>Can reduce footprint by using both surfaces</td> 2107</tr> 2108<tr> 2109<td>Handling and tooling</td> 2110<td>Usually simpler</td> 2111<td>Requires control of the first-side components during second-side processing</td> 2112</tr> 2113<tr> 2114<td>Inspection and repair</td> 2115<td>Components are accessible from one side</td> 2116<td>
2116Access and traceability must cover both sides</td> 2117</tr> 2118<tr> 2119<td>Best fit</td> 2120<td>Lower-density, cost-sensitive, serviceable products</td> 2121<td>Compact, dense, interface-rich, or space-constrained products</td> 2122</tr> 2123</tbody> 2124</table> 2125</figure> 2126<p>A double-sided build does not automatically mean twice the assembly cost. Small passive components on the underside may allow a much smaller PCB, a shorter signal path, or a cleaner connector arrangement. Conversely, placing heavy or heat-sensitive parts on the second side can complicate reflow support and inspection.</p> 2127<p>The useful comparison is therefore process-specific. If all parts fit comfortably on one side with reliable solder access and acceptable board dimensions, single-sided assembly can keep production direct. If one-sided placement creates crowding, long routes, thermal concentration, too many jumpers, or difficult soldering, using both sides can make the finished PCBA easier to manufacture consistently.</p> 2128<h2>Where Does Single Sided PCB Assembly Work Bestâand Where Does It Fall Short?</h2> 2129<p>Single sided PCB assembly works best in products with modest component density, uncomplicated interconnections, sufficient board area, and no strong need to minimize enclosure size. Common examples include simple power controls, indicator boards, appliance controls, relay boards, LED products, basic sensor interfaces, and low-complexity industrial electronics. The format is also useful when visible component identification and straightforward repair access matter.</p> 2130<p>Its limitations appear as the circuit becomes denser or more demanding. A one-sided component population can become restrictive when the product needs fine-pitch processors, large memory groups, many connectors, controlled-impedance interfaces, short high-current paths, extensive shielding, or concentrated thermal management. Forcing those functions onto one surface can enlarge the board or produce congested routing and uneven heat distribution.</p> 2131<p>Mechanical conditions matter as well. Tall components may conflict with the enclosure even if enough board area exists. Connectors may need fixed edge locations, displays or switches may have user-interface constraints, and heavy parts may require additional support. These factors can make a seemingly simple one-sided layout difficult to assemble or install.</p> 2132<p>The format is most successful when it follows the productâs real requirements rather than serving as an absolute design rule. Keeping one assembly side is worthwhile when it simplifies production without creating penalties elsewhere. When density, thermal performance, signal behavior, or enclosure limits become dominant, a double-sided or multilayer solution may deliver a more reliable and economical result.</p> 2133<h2>How Are Single Sided PCB Assemblies Inspected and Tested?</h2> 2134<p>Inspection and testing should verify both the general assembly quality and the features that are critical to the productâs function. Because components are concentrated on one side, visual access may be easier, but one-sided placement does not eliminate defects such as wrong parts, polarity errors, insufficient solder, bridging, lifted leads, contamination, or damaged through-hole barrels.</p> 2135<figure class="wp-block-image size-full"><img decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/single-sided-pcb-assembly-3.jpg" alt="single sided PCB assembly" /><figcaption class="wp-element-caption">Optical inspection and electrical probing verify different aspects of the finished assembly.</figcaption></figure> 2136<p><strong><span style="color:#0070c0">The inspection route can include:</span></strong></p> 2137<ul> 2138<li><strong>Incoming and bare-board checks</strong> for dimensions, finish, solder mask, markings, holes, and electrical continuity.</li> 2139<li><strong>Solder-paste inspection</strong> for SMT builds where paste volume and alignment influence joint formation.</li> 2140<li><strong>Automated optical inspection</strong> for component presence, orientation, polarity, placement, and visible solder conditions.</li> 2141<li><strong>Visual inspection</strong> for through-hole fill, lead protrusion, solder bridges, flux residues, mechanical damage, and workmanship details not fully covered by AOI.</li> 2142<li><strong>X-ray inspection</strong> when hidden joints or package geometry justify it; X-ray is not required merely because the assembly is single sided.</li> 2143<li><strong>Electrical testing</strong> such as continuity, shorts testing, in-circuit testing, programming, or functional testing according to the agreed product requirements.</li> 2144</ul> 2145<p>Inspection must match the technology on the board. A through-hole connector needs different acceptance evidence from a small SMT resistor, while a programmed controller requires more than a visual solder-joint check.
2145Clear test limits, fixtures, firmware versions, and pass/fail conditions allow the finished units to be evaluated consistently across production lots.</p> 2146<h2>FAQs About Single Sided PCB Assembly</h2> 2147<p><strong>Is a single sided PCB the same as single sided PCB assembly?</strong></p> 2148<p>No. A single sided PCB has one conductive copper layer, while single sided PCB assembly means all mounted components occupy one side. A multilayer board can still use a one-sided component population.</p> 2149<p><strong>Can SMT and through-hole parts be assembled on the same side?</strong></p> 2150<p>Yes. SMT and through-hole parts can share one component side, but they normally require different placement and soldering operations. Their spacing and process order must allow each operation to be completed without damaging previously mounted parts.</p> 2151<p><strong>Is single sided PCB assembly always cheaper?</strong></p> 2152<p>No. It is often economical when it eliminates second-side processing without increasing board area or manual work. A double-sided assembly may cost less overall if it reduces PCB size, jumpers, routing difficulty, special tooling, or rework.</p> 2153<p><strong>Can a multilayer PCB use single-sided component assembly?</strong></p> 2154<p>Yes. Copper-layer count and component-side count are separate choices. A multilayer PCB may keep every component on one surface to simplify assembly or meet mechanical requirements.</p> 2155<p><strong>What files are needed to quote a single sided PCB assembly?</strong></p> 2156<p>A usable quotation package normally includes PCB fabrication data, a fabrication drawing or stackup requirements, the BOM, centroid or pick-and-place data for SMT parts, assembly drawings, polarity and revision information, and the required inspection, programming, and test scope.</p> 2157<p><a href="https://www.bestpcbs.com/blog/2026/09/single-sided-pcb-assembly/">Single sided PCB assembly</a> is most valuable when one populated surface simplifies production without forcing extra board area, jumpers, or manual operations. EBest Circuit can review customer-released PCB and assembly data, manufacture the bare boards, source approved components, complete SMT and through-hole assembly, and perform agreed inspection and testing. To discuss a prototype or repeat-production build, contact <strong>[email protected]</strong>.</p> 2158 2159 </div> 2160 2161 2162 2163 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/single-sided-pcb-assembly/" rel="tag">Single Sided PCB Assembly</a>, <a href="https://www.bestpcbs.com/blog/tag/smt-assembly/" rel="tag">SMT assembly</a>, <a href="https://www.bestpcbs.com/blog/tag/through-hole-assembly-2/" rel="tag">through-hole assembly</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/bestpcb/" rel="category tag">bestpcb</a>, <a href="https://www.bestpcbs.com/blog/category/pcb-assembly-pcba/" rel="category tag">PCB Assembly / PCBA</a> | <span>Comments Closed</span></p> 2164 2165 </div> 2166 2167 2168 2169 2170 2171 2172 <div class="post-36787 post type-post status-publish format-standard hentry category-best-pcb category-pcb-technology category-pcba tag-emib-process-flow tag-emib-vs-cowos tag-emib-vs-emib-t tag-emib-t-substrate tag-intel-emib-packaging" id="post-36787"> 2173 2174 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/10/emib-t-substrate/" rel="bookmark" title="Permanent Link to EMIB-T Substrate Explained: Structure, TSV Power Delivery and Manufacturing Challenges">EMIB-T Substrate Explained: Structure, TSV Power Delivery and Manufacturing Challenges</a></h1> 2175 2176 <small>October 1st, 2026 <!-- by Love PCB --></small> 2177 2178 2179 2180 <div class="entry"> 2181 2182 <div class="yzp-no-index"></div> 2183<p>An <a href="https://www.bestpcbs.com/blog/2026/09/emib-t-substrate/">EMIB-T substrate</a> is a package substrate containing embedded silicon bridges with through-silicon vias (TSVs). The bridges provide dense connections between adjacent chips; their TSVs add a vertical power-delivery route through the silicon. This architecture supports high-bandwidth memory (HBM) and multi-chip computing packages without requiring a full-area silicon interposer. It is a semiconductor packaging structure, not a conventional system PCB. Its manufacturing challenge is integrating small silicon bridges into a much larger substrate while maintaining alignment, electrical continuity and mechanical reliability.</p> 2184<figure style="width: 100%; max-width: 600px; margin: 24px auto;"><img decoding="async" style="width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-t-substrate-hero.jpg" alt="Conceptual EMIB-T package with logic die, HBM, embedded silicon bridge and bridge TSVs" data-first-enter-image="true" /></figure> 2185<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">Key Takeaways</h2> 2186<ul> 2187<li>An <strong>EMIB-T substrate</strong> uses localized silicon bridges embedded inside the package substrate rather than placing the entire multi-die system over one large silicon interposer.</li> 2188<li>The defining development from conventional EMIB to EMIB-T is the addition of <strong>through-silicon vias (TSVs)</strong> in the bridge, enabling vertical connections and more direct power delivery.</li> 2189<li>EMIB-T combines fine-pitch lateral die-to-die routing with vertical electrical paths, which is increasingly important for high-power AI accelerators and HBM-based packages.</li> 2190<li>Intel has positioned EMIB-T for large AI and HPC packages involving HBM4/HBM4e, UCIe chiplet links, and packages extending well beyond a single reticle.</li> 2191<li>EMIB-T and CoWoS-L both use localized silicon for high-density connections, but their package architectures, interposer structures, routing approaches, and assembly flows differ.</li> 2192<li>As package dimensions and power rise, warpage, thermal behavior, power integrity, bridge alignment, TSV reliability, and known-good-die management become increasingly important.</li> 2193</ul> 2194<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">What Is an EMIB-T Substrate?</h2> 2195<p>An EMIB-T substrate integrates TSV-equipped silicon bridges into a semiconductor package substrate. EMIB means Embedded Multi-die Interconnect Bridge; EMIB-T is the TSV-enabled evolution of that technology.</p> 2196<p>Intel EMIB packaging concentrates fine interconnects where neighboring chip edges need them. The surrounding substrate c
2196arries broader package routing and mechanical support. This avoids treating every connection as though it needs the same fine-pitch silicon routing.</p> 2197<p>At EBest Circuit, our work is downstream of this packaging stage. We support system-level boards and <a href="https://www.bestpcbs.com/products/pcba.htm">PCB assembly</a>, not fabrication of the embedded bridges or EMIB-T substrates.</p> 2198<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">How Does EMIB-T Work?</h2> 2199<p>EMIB-T combines short chip-to-chip signal paths with a power route that passes vertically through the bridge. The two functions share an integration region but are not interchangeable electrical nets.</p> 2200<ul> 2201<li><strong>Data:</strong> one die connects through fine-pitch joints to bridge wiring, which reaches the neighboring die.</li> 2202<li><strong>Power:</strong> package conductors connect through bridge TSVs toward the die power connections.</li> 2203<li><strong>System interface:</strong> the rest of the package routing connects the assembled device to its external terminals.</li> 2204</ul> 2205<p>The functional diagram separates these paths. It does not represent a production cross-section or a specific pin assignment.</p> 2206<figure style="width: 100%; max-width: 600px; margin: 24px auto;"><img decoding="async" style="width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-t-interconnect-functions.jpg" alt="Functional diagram separating logic-to-HBM data communication from power delivery through bridge TSVs" /></figure> 2207<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">What Is Inside an EMIB-T Package Substrate?</h2> 2208<p>The substrate combines organic dielectric and copper routing with embedded silicon bridges and their vertical connections. The logic dies and HBM sit above this structure; external package connections sit below it.</p> 2209<div class="wp-block-table"> 2210<table> 2211<tbody> 2212<tr> 2213<td><strong>Element</strong></td> 2214<td><strong>Function</strong></td> 2215</tr> 2216<tr> 2217<td>Organic substrate structure</td> 2218<td>Mechanical support and package-level routing</td> 2219</tr> 2220<tr> 2221<td>ABF build-up dielectric and copper</td> 2222<td>Insulation between conductive routing layers in ABF-based implementations</td> 2223</tr> 2224<tr> 2225<td>Embedded silicon bridge</td> 2226<td>Localized high-density interconnect between chip edges</td> 2227</tr> 2228<tr> 2229<td>Bridge TSVs</td> 2230<td>Electrical connections through the silicon thickness</td> 2231</tr> 2232<tr> 2233<td>Fine-pitch bumps</td> 2234<td>Connections between die pads and bridge-side routing</td> 2235</tr> 2236<tr> 2237<td>Bonding and dielectric materials</td> 2238<td>Attachment, insulation and mechanical integration</td> 2239</tr> 2240<tr> 2241<td>External BGA connections, where specified</td> 2242<td>Connection from the completed package to the system PCB</td> 2243</tr> 2244</tbody> 2245</table> 2246</div> 2247<p>Ajinomoto Build-up Film provides electrical insulation for high-performance package substrates. It should not be confused with the glass-reinforced core that a particular substrate may also contain. Our <a href="https://www.bestpcbs.com/blog/2026/08/abf-substrate-shortage/">ABF substrate materials and supply guide</a> explains the wider material and sourcing context. An actual stackup still requires the package supplier’s approved material set.</p> 2248<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">EMIB vs EMIB-T: Key Differences</h2> 2249<p>The defining difference is that EMIB-T adds through-silicon connections to the embedded bridge. Conventional EMIB already provides lateral die-to-die interconnects; it does not need bridge TSVs to perform that role.</p> 2250<div class="wp-block-table"> 2251<table> 2252<tbody> 2253<tr> 2254<td><strong>Feature</strong></td> 2255<td><strong>Conventional EMIB</strong></td> 2256<td><strong>EMIB-T</strong></td> 2257</tr> 2258<tr> 2259<td>Local silicon bridge</td> 2260<td>Yes</td> 2261<td>Yes</td> 2262</tr> 2263<tr> 2264<td>Bridge TSVs</td> 2265<td>Not part of the basic architecture</td> 2266<td>Added to enable vertical connections</td> 2267</tr> 2268<tr> 2269<td>Bridge-region power access</td> 2270<td>Supplied through surrounding package routing</td> 2271<td>Additional direct path through the bridge</td> 2272</tr> 2273<tr> 2274<td>Integration requirements</td> 2275<td>Bridge placement and fine-pitch die connections</td> 2276<td>Those requirements plus TSV and backside connection integration</td> 2277</tr> 2278</tbody> 2279</table> 2280</div> 2281<figure style="width: 100%; max-width: 600px; margin: 24px auto;"><img decoding="async" style="width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-vs-emib-t.jpg" alt="Conceptual comparison of a local EMIB signal bridge and an EMIB-T bridge with TSVs" /></figure> 2282<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">Why Does EMIB-T Add TSVs to the Silicon Bridge?</h2> 2283<p>TSVs provide a more direct power route through a region that would otherwise require routing around the bridge. Intel identifies vertical power delivery with low DC and AC noise as a driver for EMIB-T, particularly for HBM.</p> 2284<p>Intel’s AI and HPC platform brief also describes bridge-integrated MIM capacitors and reduced-impedance vertical power delivery. TSVs provide a conductive path; capacitors provide local charge storage. Neither removes the need to analyze the complete power-distribution network.</p> 2285<p>Resistance contributes to DC voltage drop, while inductance affects transient voltage when current changes. Short bridge signal routes still require suitable bump geometry, reference paths and decoupling. Electrical benefit therefore depends on the complete package design, not TSV presence alone.</p> 2286<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">What Is the EMIB-T Process Flow?</h2> 2287<p>The EMIB-T process flow combines TSV-equipped bridge preparation, embedding, substrate build-up and multi-die assembly. The stages below summarize integration tasks, rather than a fixed Intel manufacturing recipe.</p> 2288<ol> 2289<li><strong>Prepare the silicon bridge:</strong> form fine routing and TSV connections, then prepare the bridge for integration. TSV formation, thinning and backside processing follow the selected bridge process.</li> 2290<li><strong>
2290Prepare substrate cavities:</strong> create the local spaces and underlying connection structures required by the package layout.</li> 2291<li><strong>Place and bond the bridges:</strong> control lateral registration, seating height and attachment quality.</li> 2292<li><strong>Build dielectric and copper layers:</strong> integrate the bridge with surrounding substrate routing and connection pads.</li> 2293<li><strong>Assemble logic dies and HBM:</strong> connect the die interfaces to the bridge and package substrate using the specified assembly flow.</li> 2294<li><strong>Reinforce and test:</strong> complete applicable underfill or bonding operations, electrical checks and reliability qualification.</li> 2295</ol> 2296<p>Intel’s EMIB product brief describes cavity embedding, attachment and dielectric/metal build-up. EMIB-T adds vertical bridge integration; exact TSV processing order and acceptance limits depend on the qualified implementation.</p> 2297<figure style="width: 100%; max-width: 600px; margin: 24px auto;"><img decoding="async" style="width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/03-emib-t-process-flow.jpg" alt="Six representative EMIB-T integration stages from bridge fabrication to testing" /></figure> 2298<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">Why Is EMIB-T Substrate Manufacturing Difficult?</h2> 2299<p>Manufacturing must align a small, rigid silicon insert with multilayer substrate wiring and die contacts through repeated processing steps. The EMIB process flow already requires this registration; EMIB-T adds the bridge’s vertical connections. Placement accuracy at one temperature does not prove alignment after bonding or subsequent thermal cycles.</p> 2300<ul> 2301<li><strong>Lateral registration:</strong> bridge pads must align with the next interconnect level.</li> 2302<li><strong>Height control:</strong> bridge and substrate surfaces must support consistent connections rather than uneven contact.</li> 2303<li><strong>Thermomechanical compatibility:</strong> different expansion behavior can produce local stress and displacement.</li> 2304<li><strong>Bonding integrity:</strong> attachment materials must bond without defects that undermine the structure.</li> 2305<li><strong>TSV reliability:</strong> evaluate copper continuity and interface stress through the specified thermal-cycling and electrical tests.</li> 2306<li><strong>Thermal design:</strong> co-design the die layout, thermal interface material and cooling hardware to manage local heat concentration.</li> 2307<li><strong>Known-good dies:</strong> screen expensive die inputs and use staged electrical checks to limit the cost of late assembly failures.</li> 2308</ul> 2309<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">What Causes EMIB-T Yield Challenges?</h2> 2310<p>Misregistration, nonuniform height and bonding defects can make otherwise usable bridge and substrate components fail after integration. More interfaces also create more opportunities for a defect to interrupt an electrical path.</p> 2311<p>A September 23, 2026 TrendForce News report, citing supply-chain sources, put EMIB substrate yield at approximately 45%. Its reported targets were 50% in Q4 2026 and 60% in Q1 2027. These are reported substrate-stage figures and future targets, not Intel-published production data or a verified yield for every EMIB-T package.</p> 2312<p>The September 2026 supply-chain report specifically discussed thermal-expansion mismatch, bridge positioning and bubbles in non-conductive film beneath bridge TSV connections. Those are reported production challenges, not a published defect breakdown across all suppliers.</p> 2313<p>A useful yield discussion must identify the tested population. Bridge-wafer yield, integrated-substrate yield and final electrical package yield have different denominators. A quoted percentage without its process stage, product complexity and test criteria cannot reliably predict delivered device availability.</p> 2314<figure style="width: 100%; max-width: 600px; margin: 24px auto;"><img decoding="async" style="width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-t-integration-challenges.jpg" alt="Illustrative bridge integration defects showing misalignment, warpage and bonding voids" /></figure> 2315<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">EMIB vs CoWoS: What are Differences?</h2> 2316<p>EMIB embeds local silicon bridges in the package substrate; TSMC describes CoWoS as a family of interposer-based technologies. CoWoS-S uses a continuous silicon interposer, whereas CoWoS-L combines an RDL interposer with local silicon interconnects.</p> 2317<div class="wp-block-table"> 2318<table> 2319<tbody> 2320<tr> 2321<td><strong>Architecture</strong></td> 2322<td><strong>High-density interconnect structure</strong></td> 2323</tr> 2324<tr> 2325<td>EMIB-T</td> 2326<td>Local TSV-equipped silicon bridges embedded in the package substrate</td> 2327</tr> 2328<tr> 2329<td>CoWoS-S</td> 2330<td>Silicon interposer spanning the integrated die arrangement</td> 2331</tr> 2332<tr> 2333<td>CoWoS-L</td> 2334<td>RDL-based interposer incorporating local silicon interconnects</td> 2335</tr> 2336</tbody> 2337</table> 2338</div> 2339<p>Local bridges reduce the silicon area devoted to interconnection, but add integration demands at each bridge location. A larger silicon interposer supports routing across a wider area; its manufacturing approach is different. Neither description proves that one complete package is always cheaper or has better yield.</p> 2340<p>For a closer structural comparison, our <a href="https://www.bestpcbs.com/blog/2026/09/cowos-l/">CoWoS-L explanation</a> distinguishes local silicon interconnects from the surrounding RDL. CoWoS-L is not an all-silicon interposer, and it is not simply another name for EMIB-T.</p> 2341<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">How Does EMIB-T Support HBM4, HBM4e and UCIe?</h2> 2342<p>EMIB-T supports dense memory and chiplet interfaces by combining short lateral silicon routes with vertical power access through the bridge. AI accelerators and HPC processors need both: more data connections alone do not solve the power demands of the connected dies.</p> 2343<ul> 2344<li><strong>HBM4/HBM4e:</strong>
2344 wide logic-to-memory interfaces need dense routing close to the compute die. Bridge TSVs add power paths through that crowded region.</li> 2345<li><strong>UCIe:</strong> short chiplet links need controlled interconnect geometry and return paths, alongside the power network.</li> 2346<li><strong>Large packages:</strong> placement and routing must be evaluated together with thermal and mechanical behavior.</li> 2347</ul> 2348<p>In its ECTC 2026 technology update, Intel reported these development results:</p> 2349<ul> 2350<li>25 μm first-level interconnect bump pitch.</li> 2351<li>120 à 120 mm package dimensions.</li> 2352<li>More than nine reticle areas of compute and memory silicon in one package.</li> 2353<li>Signal and power co-optimization supporting 12 Gb/s HBM4e and 64 Gb/s UCIe transmission.</li> 2354</ul> 2355<p>These are technology-development results, not universal specifications for every production package. Separately, Synopsys’ EMIB-T design-flow discussion describes large-design demands including footprints of 120 à 180 mm. That design context should not be combined with Intel’s demonstration dimensions into a single qualified manufacturing range.</p> 2356<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">Where Is EMIB-T Used in AI and HPC Packaging?</h2> 2357<p>EMIB-T is designed mainly for large AI and HPC packages that integrate multiple compute dies, HBM stacks, and high-speed chiplet interfaces.</p> 2358<p>Typical applications include:</p> 2359<ul> 2360<li>AI training accelerators;</li> 2361<li>AI inference processors;</li> 2362<li>HPC accelerators;</li> 2363<li>multi-die GPU or XPU packages;</li> 2364<li>chiplet-based CPUs;</li> 2365<li>UCIe-based heterogeneous processors;</li> 2366<li>multi-HBM compute modules;</li> 2367<li>data-center processors.</li> 2368</ul> 2369<p>The package has to move large volumes of data between dies, feed high current to compute silicon, connect several HBM stacks, and control thermal and mechanical stress at the same time.</p> 2370<p>EMIB-T is particularly relevant where localized high-density silicon routing is needed but using one continuous silicon interposer across the whole package is not the preferred architecture.</p> 2371<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">Is an EMIB-T Substrate the Same as a PCB?</h2> 2372<p>No. The EMIB-T substrate is part of the semiconductor package; the system PCB connects that completed package to the rest of the electronic system.</p> 2373<p>A TSV passes through silicon. A package-substrate microvia passes through a dielectric layer. A PCB via connects copper layers in a board. They differ in materials, dimensions and manufacturing processes, even though all provide electrical connections between levels.</p> 2374<p>For a BGA-mounted device, the board land pattern comes from the external ball map and package drawingânot from the pitch of the bridge’s internal microbumps. Using an internal packaging dimension as a PCB footprint dimension would address the wrong interface.</p> 2375<figure style="width: 100%; max-width: 600px; margin: 24px auto;"><img decoding="async" style="width: 100%; max-width: 600px; max-height: 400px; height: auto; object-fit: contain;" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/emib-t-package-to-pcb.jpg" alt="Exploded conceptual view separating the chip package, external BGA connections and larger system PCB" /></figure> 2376<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">FAQ About EMIB-T Substrates</h2> 2377<p><strong>Is EMIB-T the same as EMIB-M?</strong></p> 2378<p>No. Intel’s technology brief uses EMIB-M for bridge-integrated metal-insulator-metal capacitors and EMIB-T for the TSV-enabled solution. Later descriptions of EMIB-T also discuss MIM capacitors. TSVs and capacitors perform different functions, so the names should not be treated as interchangeable material grades.</p> 2379<p><strong>Does EMIB-T require a glass-core substrate?</strong></p> 2380<p>No. Public Intel descriptions include organic-substrate implementations. EMIB-T identifies the embedded-bridge technology, not a universal core material. A proposed glass-core implementation would require its own approved stackup and reliability evidence; it should not be assumed from the EMIB-T name.</p> 2381<p><strong>Is EMIB-T the same as Foveros?</strong></p> 2382<p>No. EMIB-T provides local bridge connections between neighboring dies, while Foveros technologies support other integration arrangements, including vertical die stacking. Intel describes combining the technologies in
2382EMIB 3.5D. A combined package does not make their interconnect structures identical.</p> 2383<p><strong>Can an existing package move to EMIB-T without redesign?</strong></p> 2384<p>Not automatically. Die interfaces, bump assignments, power paths and mechanical constraints need to match the chosen packaging flow. Synopsys’ reference-flow announcement includes early bump and TSV planning and multiphysics analysis, illustrating why a technology migration is an engineering project rather than a material substitution.</p> 2385<p><strong>Can PCB-level X-ray inspection certify the internal silicon bridge?</strong></p> 2386<p>No. Inspecting board-level solder joints does not qualify buried package interconnects. Package acceptance requires the package supplier’s electrical and reliability evidence. PCB assembly inspection evaluates the board-level work and cannot replace semiconductor-package qualification.</p> 2387<h2 style="font-size: 26px; line-height: 1.35; font-weight: bold;">What Does EMIB-T Mean for PCB and PCBA Projects?</h2> 2388<p>For downstream manufacturing, the practical requirement is a released package specification and a board design matched to it. The packaging architecture alone does not set PCB layer count, laminate grade or assembly temperature.</p> 2389<ul> 2390<li><strong>Footprint and routing:</strong> confirm the package drawing, ball map and approved land pattern before <a href="https://www.bestpcbs.com/design-guide/index.htm">PCB design review</a>.</li> 2391<li><strong>Power and thermal requirements:</strong> use device-level current and cooling specifications to review the board power network and mechanical clearances.</li> 2392<li><strong>Assembly plan:</strong> check the supplied component’s handling, moisture sensitivity and mounting instructions, together with the agreed inspection and functional-test scope.</li> 2393</ul> 2394<p>At EBest Circuit, we support PCB fabrication, component sourcing and PCBA projects, with suitability confirmed against the actual design. Send the processor package specification, PCB files, BOM, quantities and test requirements to <a href="mailto:[email protected]">[email protected]</a> for a project-specific review.</p> 2395 2396 </div> 2397 2398 2399 2400 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/emib-process-flow/" rel="tag">emib process flow</a>, <a href="https://www.bestpcbs.com/blog/tag/emib-vs-cowos/" rel="tag">emib vs cowos</a>, <a href="https://www.bestpcbs.com/blog/tag/emib-vs-emib-t/" rel="tag">emib vs emib-t</a>, <a href="https://www.bestpcbs.com/blog/tag/emib-t-substrate/" rel="tag">EMIB-T substrate</a>, <a href="https://www.bestpcbs.com/blog/tag/intel-emib-packaging/" rel="tag">intel emib packaging</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/pcb-technology/" rel="category tag">PCB Technology</a>, <a href="https://www.bestpcbs.com/blog/category/pcba/" rel="category tag">PCBA</a> | <a href="https://www.bestpcbs.com/blog/2026/10/emib-t-substrate/#respond">No Comments »</a></p> 2401 2402 </div> 2403 2404 2405 2406 2407 2408 2409 <div class="post-36670 post type-post status-publish format-standard hentry category-pcb-knowledge tag-pcb-footprint tag-smt-assembly tag-solder-joint-inspection tag-ssop-package" id="post-36670"> 2410 2411 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/10/ssop-package/" rel="bookmark" title="Permanent Link to What Is SSOP Package? Dimensions, PCB Footprint, Soldering, and Applications">What Is SSOP Package? Dimensions, PCB Footprint, Soldering, and Applications</a></h1> 2412 2413 <small>October 1st, 2026 <!-- by Jessica, Jessica --></small> 2414 2415 2416 2417 <div class="entry"> 2418 2419 <div class="yzp-no-index"></div> 2420<style id="ssop-post-36670-fixes"> 2421body.postid-36670 h1._title { word-break: normal !important; overflow-wrap: normal !important; hyphens: none !important; }<br /> 2422body.postid-36670 .entry h2 { border-left: 5px solid #1266d6 !important; padding-left: 14px !important; background: transparent !important; }<br /> 2423body.postid-36670 .entry figure.wp-block-table { width: 100% !important; overflow: visible !important; }<br /> 2424body.postid-36670 .entry table { width: 100% !important; border: 1px solid #222 !important; border-collapse: collapse !important; table-layout: fixed !important; }<br /> 2425body.postid-36670 .entry th, body.postid-36670 .entry td { border: 1px solid #222 !important; padding: 10px 8px !important; text-align: left !important; vertical-align: top !important;
2425 overflow-wrap: anywhere !important; word-break: normal !important; }<br /> 2426@media (max-width: 520px) {<br /> 2427 body.postid-36670 .entry table { font-size: 12px !important; }<br /> 2428 body.postid-36670 .entry th, body.postid-36670 .entry td { padding: 6px 3px !important; }<br /> 2429}<br /> 2430</style> 2431<p>An <a href="https://www.bestpcbs.com/blog/2026/10/ssop-package/">SSOP package</a>, or Shrink Small Outline Package, is a surface-mount IC package with gull-wing leads on two sides. It gives designers a compact, leaded package whose solder joints remain visible around the body.</p> 2432<p>SSOP is a package family, not one fixed mechanical outline. Two parts described as SSOP may use different body widths, lead spans, pitches, heights, and PCB land patterns, so the exact package code and manufacturer’s drawing must guide footprint design and assembly.</p> 2433<figure><img loading="lazy" decoding="async" class="aligncenter size-full" style="display: block; width: 100%; max-width: 600px; height: auto; margin: 0 auto;" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/ssop-package-hero-af123608fb.jpg" alt="SSOP package, elongated fine-pitch IC mounted on a complete PCB module at an electronics inspection bench" width="600" height="400" /></figure> 2434<h2 id="what-is-ssop-package">What Is SSOP Package?</h2> 2435<p><strong>SSOP stands for Shrink Small Outline Package, a compact surface-mount IC package with gull-wing leads arranged along two opposite sides.</strong> Compared with a standard SOIC of similar pin count, an SSOP generally uses a narrower body and finer lead spacing, reducing PCB area while keeping the solder joints exposed for optical inspection and rework.</p> 2436<p>SSOP describes a package family rather than one interchangeable outline. Confirm the exact manufacturer’s package code and drawing before choosing a PCB footprint because body width, lead pitch, overall span, height, and land-pattern requirements can differ. The practical tradeoff is greater board density with less assembly margin, so stencil design, placement accuracy, and solder-bridge control need closer attention.</p> 2437<h2 id="ssop-package-dimensions">What Are the Standard SSOP Package Dimensions?</h2> 2438<p><strong>There is no single set of SSOP package dimensions for every device.</strong> The same SSOP label covers multiple JEDEC outlines, body widths, heights, lead counts, and pitches. Use the package code on the exact component datasheet before selecting or creating a footprint.</p> 2439<p>The examples below from the NXP SSOP package index show how dimensions can vary within one manufacturer’s package family. The body column reports package length à body width à the height value listed by NXP, which may be nominal or maximum depending on the outline.</p> 2440<figure class="wp-block-table"> 2441<table> 2442<tbody> 2443<tr> 2444<td><strong>Package Example</strong></td> 2445<td><strong>Pitch</strong></td> 2446<td><strong>Body (mm)</strong></td> 2447</tr> 2448<tr> 2449<td>SSOP16, SOT338-1</td> 2450<td>0.65 mm</td> 2451<td>6.2 à 5.3 à 2.0</td> 2452</tr> 2453<tr> 2454<td>SSOP20, SOT339-1</td> 2455<td>0.65 mm</td> 2456<td>7.2 à 5.3 à 2.0</td> 2457</tr> 2458<tr> 2459<td>SSOP24, SOT340-1</td> 2460<td>0.65 mm</td> 2461<td>8.2 à 5.3 à 2.0</td> 2462</tr> 2463<tr> 2464<td>SSOP28, SOT341-1</td> 2465<td>0.65 mm</td> 2466<td>10.2 à 5.3 à 2.0</td> 2467</tr> 2468<tr> 2469<td>SSOP16, SOT519-1</td> 2470<td>0.635 mm</td> 2471<td>4.9 à 3.9 à 1.73</td> 2472</tr> 2473<tr> 2474<td>SSOP48, SOT370-1</td> 2475<td>0.635 mm</td> 2476<td>15.9 à 7.5 à 2.8</td> 2477</tr> 2478</tbody> 2479</table> 2480</figure> 2481<p>These examples explain why SSOP-16 package dimensions or SSOP-20 package dimensions cannot be inferred from pin count alone. A 16-pin SSOP package can belong to a 5.3 mm-wide, 0.65 mm family or a 3.9 mm-wide, 0.635 mm family. Likewise, an SSOP-28 package should be checked by its package drawing rather than by an unqualified library name.</p> 2482<h2 id="ssop-lead-pitch">What Lead Pitch Does an SSOP Package Use?</h2> 2483<p><strong>A 0.65 mm lead pitch is common, but it is not universal.</strong> Official manufacturer package libraries also list 0.635 mm and 0.64 mm SSOP families, so the pitch must come from the exact package drawing or orderable-part datasheet.</p> 2484<p>Pitch is the center-to-center distance between adjacent leads. It controls pad spacing, solder-mask geometry, routing escape, stencil behavior, placement tolerance, and the optical resolution needed to detect bridges. Do not assume that a 0.65 mm footprint is compatible with a 0.635 mm package because the difference looks small; the offset accumulates across the lead row.</p> 2485<p>Confirm the pitch together with body width, lead count, overall lead span, lead width, lead length, and package height. Use that c
2485omplete set of dimensions, not the pitch alone, to choose or build the PCB land pattern.</p> 2486<h2 id="ssop-pcb-footprint">How Should You Design an SSOP PCB Footprint?</h2> 2487<p><strong>Build or select the footprint from the exact package code and its recommended land pattern.</strong> Component lead dimensions describe the part; they are not the same as the PCB pad dimensions needed to solder it.</p> 2488<ol> 2489<li><strong>Confirm the exact package code:</strong> Start with the manufacturer’s part number, package suffix, pin count, and drawing code. A library name such as âSSOP-20â is not specific enough on its own.</li> 2490<li><strong>Check pitch and lead geometry:</strong> Read the specified pitch and the dimensional limits for lead width and length, body width and length, overall lead span, standoff, and coplanarity. A nominal body size alone does not show where every lead can land.</li> 2491<li><strong>Use the recommended land pattern:</strong> Prefer the component manufacturer’s current recommendation when one is available. For example, TI’s DB0028A drawing shows 0.45 Ã 1.85 mm lands on 0.65 mm pitch for that specific 28-lead outline, not for every SSOP-28 package.</li> 2492<li><strong>Check solder mask and paste openings:</strong> Confirm that the fabricator can hold the intended mask web and that stencil apertures suit the paste and assembly process. Excess paste can increase bridging, while too little paste can produce opens or weak joints.</li> 2493<li><strong>Verify pin 1 and component orientation:</strong> Align the footprint marker, silkscreen, courtyard, centroid rotation, and assembly drawing. Leave enough access around both lead rows for optical inspection and rework.</li> 2494</ol> 2495<p>Never assume that two SSOP devices with the same pin count can share a footprint. Compare the complete drawing and recommended land pattern before reusing a library part.</p> 2496<h2 id="difference-between-soic-and-ssop-package">What Is the Difference Between SOIC and SSOP Packages?</h2> 2497<p><strong>SSOP is usually the better choice when board area is tight, while SOIC generally offers more assembly and rework margin.</strong> The table compares the points that most often affect package selection; exact dimensions and performance still depend on the orderable device and its package drawing.</p> 2498<figure class="wp-block-table"> 2499<table> 2500<thead> 2501<tr> 2502<th>What Users Care About</th> 2503<th>SOIC</th> 2504<th>SSOP</th> 2505</tr> 2506</thead> 2507<tbody> 2508<tr> 2509<td>PCB area</td> 2510<td>Usually needs more board area for a similar lead count</td> 2511<td>Usually uses less board area for a similar lead count</td> 2512</tr> 2513<tr> 2514<td>Common lead pitch</td> 2515<td>Often 1.27 mm</td> 2516<td>Often 0.65, 0.635, or 0.64 mm</td> 2517</tr> 2518<tr> 2519<td>Assembly margin</td> 2520<td>Wider lead spacing gives more print and placement margin</td> 2521<td>Tighter spacing needs closer stencil, placement, and reflow control</td> 2522</tr> 2523<tr> 2524<td>Prototyping and hand soldering</td> 2525<td>Generally easier to place and solder manually</td> 2526<td>Feasible with suitable tools, magnification, and operator control</td> 2527</tr> 2528<tr> 2529<td>Inspection and rework</td> 2530<td>Exposed leads are easier to see and access</td> 2531<td>Exposed leads remain visible, but tighter spacing makes bridges and rework more demanding</td> 2532</tr> 2533<tr> 2534<td>Footprint compatibility</td> 2535<td>Not interchangeable with SSOP without checking the exact drawing and land pattern</td> 2536<td>Needs its own checked land pattern rather than an assumed SOIC footprint</td> 2537</tr> 2538</tbody> 2539</table> 2540</figure> 2541<p>SOIC is often easier to prototype, inspect, and rework when board area is available. SSOP is useful when density matters and the assembly process can control the finer pitch. Neither is a drop-in substitute for the other, even when the pin count and electrical function appear to match. The <a href="https://www.bestpcbs.com/blog/2026/07/soic-package/">SOIC package</a> guide provides additional SOIC-specific detail.</p> 2542<h2 id="difference-between-ssop-and-tssop-packages">What Is the Difference Between SSOP and TSSOP Packages?</h2> 2543<p><strong>TSSOP is a thinner small-outline package family and is often more compact than a comparable SSOP, but the names alone do not prove footprint compatibility.</strong> In TI’
2543s 20-pin package comparison, the DB SSOP has a 2.00 mm maximum height, while the PW TSSOP has a 1.20 mm maximum and occupies less footprint area. That example illustrates the family difference; it does not define every SSOP or TSSOP.</p> 2544<p>Pitch is not a reliable shortcut because both families contain multiple outlines. NXP listings, for example, include TSSOP packages at 0.65 mm and 0.5 mm pitch, while its SSOP listings include 0.65 mm and 0.635 mm examples. Before changing packages, compare pitch, body width and length, lead span, lead dimensions, height, pinout, and the recommended land pattern from the exact device drawings.</p> 2545<p>The same pin count or device family does not make an SSOP and TSSOP mechanically interchangeable. Treat a package change as a PCB footprint check, not as a name-based substitution.</p> 2546<h2 id="ssop-package-applications">Where Are SSOP Packages Commonly Used?</h2> 2547<p><strong>SSOP packages are common where a dual-row leaded IC must fit into limited board space while keeping its joints optically accessible.</strong> The package appears across many device classes; it is not tied to a single circuit function.</p> 2548<ul> 2549<li><strong>Logic and I/O:</strong> Buffers, latches, bus-interface devices, and I/O expanders are often offered in this compact leaded format.</li> 2550<li><strong>Data conversion:</strong> ADCs, DACs, and mixed-signal ICs may use SSOP when the layout needs moderate pin density and visible leads.</li> 2551<li><strong>Interfaces and communications:</strong> Transceivers, line drivers, and serial-interface devices are common candidates when routing space is limited but optical inspection still matters.</li> 2552<li><strong>Analog and control:</strong> Op-amps, sensor interfaces, controllers, and clock devices are available in SSOP options when their pin count and thermal needs fit the outline.</li> 2553<li><strong>Compact equipment:</strong> Industrial controls, consumer electronics, audio/video products, and communication hardware use SSOP when the smaller mounting area justifies the finer-pitch assembly process.</li> 2554</ul> 2555<p>In practice, the exact device and mechanical outline should drive the decision. An application label by itself is not a reason to choose SSOP.</p> 2556<h2 id="selecting-an-ssop-package">What Should You Consider When Selecting an SSOP Package?</h2> 2557<p><strong>Select the electrical device first, then verify that its exact SSOP option fits the board, assembly process, inspection plan, and supply strategy.</strong> Package size cannot compensate for an incorrect function, rating, or lifecycle choice.</p> 2558<ul> 2559<li><strong>Does the IC meet the electrical requirement?</strong> Confirm function, pinout, ratings, speed, accuracy, interfaces, temperature range, and any thermal limits for the real board conditions.</li> 2560<li><strong>Does the exact outline fit the available PCB space?</strong> Check the package suffix, lead count, body size, lead span, height, courtyard, and routing access rather than comparing body width alone.</li> 2561<li><strong>Can the PCB and SMT process handle the pitch?</strong> Match the pad, mask, stencil, placement, and reflow requirements to the fabricator and assembler’s capabilities.</li> 2562<li><strong>Can the package be inspected and reworked?</strong> Allow optical access to both lead rows and enough surrounding space for the planned inspection and rework tools.</li> 2563<li><strong>Will the exact package remain available?</strong> Check the component’s lifecycle, authorized supply options, and qualified alternatives early enough to avoid a late footprint change.</li> 2564</ul> 2565<h2 id="ssop-package-soldering">How Is an SSOP Package Soldered to a PCB?</h2> 2566<p><strong>Production SSOP assembly normally uses solder-paste printing, pick-and-place, controlled reflow, and inspection.</strong> Fine lead spacing makes print volume and lead-to-pad alignment more sensitive than they are for a wider-pitch package, but there is no universal SSOP temperature profile.</p> 2567<ol> 2568<li><strong>Print the solder paste:</strong> Align the stencil apertures with the pads and control deposit volume. Too much paste raises bridge risk; missing or incomplete deposits raise open-joint risk.</li> 2569<li><strong>Place the component:</strong> Match pin 1 and align both lead rows with their pads. A placement offset can push one row toward bridging while leaving too little overlap on the other.</li> 2570<li><strong>Reflow the assembly:</strong> Set the profile from the solder alloy and paste guidance, PCB thermal mass, and the component’s temperature limit. Board construction and nearby components change heating behavior, so a package name cannot supply one universal profile.</li> 2571<li><strong>Inspect the joints:</strong> After reflow, check the exposed gull-wing leads for bridging, opens, misalignment, lifted leads, and poor wetting, then use electrical testing where product risk and test access justify it.</li> 2572</ol> 2573<p>Footprint dimensions, package and board tolerances, placement accuracy, flatness, solder paste, and stencil behavior work together. A correct package drawing cannot compensate for the wrong land pattern or a shifted paste print.</p> 2574<h2 id="ssop-assembly-problems">What Assembly Problems Can Occur With SSOP Packages?</h2> 2575<p><strong>The most common SSOP assembly problems are bridges, opens, misalignment, lifted leads, poor wetting, and orientation errors.</strong> Start with what is visible, then check the process condition most likely to have produced it.</p> 2576<figure class="wp-block-table"> 2577<table> 2578<tbody> 2579<tr> 2580<td><strong>Observation</strong></td> 2581<td><strong>Likely Cause</strong></td> 2582<td><strong>First Check</strong></td> 2583</tr> 2584<tr> 2585<td>Solder bridge</td> 2586<td>Excess or shifted paste, placement offset, pad or mask mismatch</td> 2587<td>Paste deposits, stencil apertures, placement image, and pad spacing</td> 2588</tr> 2589<tr> 2590<td>Open or low-solder joint</td> 2591<td>Missing paste, poor transfer, bent lead, coplanarity error, or weak wetting</td> 2592<td>Paste deposit, lead plane, pad finish, profile, and visible wetting</td> 2593</tr> 2594<tr> 2595<td>Component skew</td> 2596<td>Unequal deposits, placement error, or asymmetric reflow forces</td> 2597<td>Pad symmetry, deposit balance, and pre-reflow placement</td> 2598</tr> 2599<tr> 2600<td>Lifted lead</td> 2601<td>Lead damage, poor coplanarity, handling stress, or pad-height variation</td> 2602<td>Incoming lead condition, seating plane, board flatness, and local joint gap</td> 2603</tr> 2604<tr> 2605<td>Poor wetting</td> 2606<td>Oxidation, contamination, unsuitable profile, or expired/incorrect material</td> 2607<td>Lead and pad finish, paste condition, cleanliness, and reflow profile</td> 2608</tr> 2609<tr> 2610<td>Wrong orientation</td> 2611<td>Ambiguous marking or inconsistent library, CPL, feeder, and drawing data</td> 2612<td>Pin 1 on the part, footprint, placement data, and AOI model</td> 2613</tr> 2614</tbody> 2615</table> 2616</figure> 2617<p>Do not repair the symptom before confirming the cause. Removing a bridge may restore continuity on one board, but a shifted stencil or incorrect footprint can repeat the same defect across the lot.</p> 2618<h2 id="ssop-solder-joint-inspection">How Should SSOP Solder Joints Be Inspected?</h2> 2619<p><strong>
2619Inspect SSOP joints with visual or automated optical methods first because the gull-wing leads and fillets are exposed.</strong> Judge the joints against the applicable product requirement and assembly standard rather than a generic online photograph.</p> 2620<ul> 2621<li><strong>Confirm identity and orientation:</strong> Verify the part marking, package suffix, pin 1, polarity where applicable, and seating position before judging individual joints.</li> 2622<li><strong>Inspect the lead rows:</strong> Check lead-to-pad alignment, unintended connections, insufficient solder, lifted or damaged leads, visible wetting, and consistent fillet formation at the toe and heel regions that can be seen.</li> 2623<li><strong>Use AOI for repeatable coverage:</strong> Program the correct package geometry and joint criteria. AOI can compare every visible lead quickly, but lighting, library setup, board contrast, and obstructions affect its results.</li> 2624<li><strong>Apply X-ray only when justified:</strong> X-ray is not automatically required for an ordinary exposed-lead SSOP joint. Use it when a hidden feature, overlapping structure, adjacent bottom-terminated device, or failure investigation cannot be resolved optically.</li> 2625<li><strong>Add electrical testing where needed:</strong> Continuity, shorts, in-circuit, or functional testing can reveal failures that appearance alone cannot prove. Electrical testing complements solder-joint inspection; it does not replace it.</li> 2626</ul> 2627<p>IPC-A-610 is widely used for electronic-assembly acceptance, but the applicable revision and class must come from the product or customer requirement. Do not infer pass limits from a photograph.</p> 2628<h2 id="faqs-about-ssop-packaging">FAQs About SSOP Packaging</h2> 2629<p><strong>Q1: What do codes such as DB and DBQ mean on an SSOP listing?</strong></p> 2630<p><strong>A1: They are manufacturer-specific package designators, not interchangeable names for one outline.</strong> For example, two SSOP codes can indicate different body widths or lead pitches. Match the code on the orderable part number to the drawing in the same datasheet.</p> 2631<p><strong>Q2: Can an SSOP IC plug directly into a solderless breadboard?</strong></p> 2632<p><strong>A2: No.</strong> SSOP is a surface-mount package, and its fine lead spacing does not match a standard 2.54 mm breadboard grid. For prototyping, solder the IC to a suitable SSOP-to-DIP adapter or use a purpose-built carrier board.</p> 2633<p><strong>Q3: What should you check before buying an SSOP-to-DIP adapter?</strong></p> 2634<p><strong>A3: Match the adapter to the exact pin count, lead pitch, body width, lead span, pad layout, and pin 1 orientation.</strong> A board labeled only âSSOP-16â may not fit every 16-lead SSOP outline.</p> 2635<p><strong>Q4: Does the SSOP name guarantee RoHS compliance?</strong></p> 2636<p><strong>A4: No.</strong> SSOP describes the package family, not the terminal finish or environmental status. Check the exact orderable part number, material declaration, and applicable compliance documentation.</p> 2637<p><strong>Q5: How should moisture-sensitive SSOP parts be stored before reflow?</strong></p> 2638<p><strong>A5: Follow the moisture-sensitivity label and the component manufacturer’s handling instructions.</strong> Keep unopened parts in their specified moisture-barrier packaging. After opening the bag, observe the stated floor life and use controlled dry storage or baking only when the product instructions and applicable J-STD-033 requirements call for it.</p> 2639<h2 id="conclusion">Conclusion</h2> 2640<p>The safest SSOP design starts with the exact orderable part, not a generic library name. Before PCB layout, confirm its pitch, body dimensions, lead geometry, package code, and recommended land pattern. That work gives printing, placement, soldering, and inspection a sound starting point.</p> 2641<p>If your PCB uses SSOP or another fine-pitch SMT package, send the part number, datasheet, PCB files, BOM, quantity, and assembly requirements to <a href="mailto:[email protected]">[email protected]</a> for review and quotation.</p> 2642 2643 </div> 2644 2645 2646 2647 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/pcb-footprint/" rel="tag">pcb footprint</a>, <a href="https://www.bestpcbs.com/blog/tag/smt-assembly/" rel="tag">SMT assembly</a>, <a href="https://www.bestpcbs.com/blog/tag/solder-joint-inspection/" rel="tag">solder joint inspection</a>, <a href="https://www.bestpcbs.com/blog/tag/ssop-package/" rel="tag">SSOP Package</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/pcb-knowledge/" rel="category tag">PCB Knowledge</a>
2647 | <a href="https://www.bestpcbs.com/blog/2026/10/ssop-package/#respond">No Comments »</a></p> 2648 2649 </div> 2650 2651 2652 2653 2654 2655 2656 <div class="post-36677 post type-post status-publish format-standard hentry category-ai-pcb category-best-pcb category-bestpcb tag-ai-server-power-board tag-ai-server-power-supply tag-power-delivery-board" id="post-36677"> 2657 2658 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/10/ai-server-power-board/" rel="bookmark" title="Permanent Link to AI Server Power Board for 800 VDC Power Delivery">AI Server Power Board for 800 VDC Power Delivery</a></h1> 2659 2660 <small>October 1st, 2026 <!-- by zeng, liuyan --></small> 2661 2662 2663 2664 <div class="entry"> 2665 2666 <div class="yzp-no-index"></div> 2667<p><a href="https://www.bestpcbs.com/blog/2026/09/ai-server-power-board/">AI server power board</a> is an emerging term for a board that converts or distributes high-density power inside an AI server, compute tray, or closely related power assembly. It is not automatically the same as a complete server PSU, rack PDU, motherboard, or power shelf. The exact meaning depends on where the board sits in the power chain and which voltage conversion or distribution function it performs.</p> 2668<p>EBest Circuit supports high-current PCB fabrication, component sourcing, PCBA, inspection, and agreed board-level testing for customer-approved power electronics. If you are preparing a high-power DC-DC board or power delivery board for production, send the released PCB files, BOM, mechanical information, and test requirements to <strong>[email protected]</strong> for a manufacturing review.</p> 2669<figure class="wp-block-image size-large wp-image-36672"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/ai-server-power-board-1.jpg" alt="AI server power board" width="1200" height="800" /></figure> 2670<h2>What Is an AI Server Power Board?</h2> 2671<p>An AI server power board is a PCB or PCBA that converts or distributes power near the computing hardware. Depending on the architecture, it may carry an intermediate bus voltage, step that voltage down, or connect a power shelf to GPU, accelerator, CPU, and memory loads.</p> 2672<p><strong><span style="color: #0070c0;">The term needs context because several assemblies in a server handle power:</span></strong></p> 2673<ul> 2674<li>a rack PDU distributes facility power to equipment.</li> 2675<li>a power shelf contains multiple power supplies and may provide redundancy.</li> 2676<li>a server power supply converts AC or high-voltage DC into an intermediate DC output.</li> 2677<li>a power delivery board performs a board-level conversion or distribution function closer to the load.</li> 2678<li>voltage regulator modules provide the final low-voltage, high-current rails used by processors and memory.</li> 2679</ul> 2680<p>An AI server power board may therefore be a large distribution board, a compact high-ratio DC-DC board, or part of a tray-level power assembly. Its identity comes from its electrical function and positionânot simply from being a PCB installed in an AI server.</p> 2681<h2>Where Does a Power Delivery Board Fit in the AI Server Power Architecture?</h2> 2682<p>A power delivery board normally sits between the server’s intermediate DC supply and the final point-of-load regulators. Power reaches an accelerator through a chain such as:</p> 2683<p><strong>Facility input â rack distribution â power shelf or PSU â intermediate DC bus â power delivery board â point-of-load regulation â GPU or accelerator</strong></p> 2684<p>Moving conversion closer to the compute tray shortens high-current, low-voltage paths. Because conductor loss rises with the square of current, carrying power upstream at a higher voltage can reduce current and distribution loss.</p> 2685<p>The board may also provide input protection, controlled startup, isolation, voltage conversion, current sharing, sensing, and connections to busbars or cable assemblies. These functions vary by platform. A board described only as an âAI server power boardâ still needs an input range, output range, rated power, isolation requirement, cooling method, and mechanical envelope before it can be treated as a defined product.</p> 2686<h2>AI Server Power Supply vs Power Delivery Board: What Is the Difference?</h2> 2687<p>An <a href="https://www.bestpcbs.com/blog/2026/05/custom-pcb-power-supply/">AI server power supply</a> usually creates the intermediate DC supply. A power delivery board converts or distributes that power closer to the computing load. A point-of-load regulator then produces the final processor rails.</p> 2688<figure class="wp-block-table"> 2689<table> 2690<tbody> 2691<tr> 2692<td><strong>Assembly</strong></td> 2693<td><strong>Main role</strong></td> 2694<td><strong>Usual location</strong></td> 2695</tr> 2696<tr> 2697<td>
2697Server PSU</td> 2698<td>Creates an intermediate DC supply</td> 2699<td>Power shelf or server input</td> 2700</tr> 2701<tr> 2702<td>Power delivery board</td> 2703<td>Converts or distributes power near the load</td> 2704<td>Compute tray or accelerator assembly</td> 2705</tr> 2706<tr> 2707<td>Point-of-load regulator</td> 2708<td>Produces final processor rails</td> 2709<td>Compute board</td> 2710</tr> 2711</tbody> 2712</table> 2713</figure> 2714<p>The distinction affects manufacturing. A complete PSU usually includes an enclosure, fan or cold plate, safety spacing, input/output connectors, and its own control electronics. A power delivery board may instead depend on the server chassis for cooling, insulation coordination, busbar support, and mechanical protection.</p> 2715<p>Calling every power-related assembly a PSU hides these differences. The PCB stackup, copper weight, connector system, cooling interface, assembly sequence, and test fixture all depend on the board’s actual place in the architecture.</p> 2716<h2>Why Is 800 VDC Power Delivery Moving Closer to the Compute Tray?</h2> 2717<p>It is moving closer to the compute tray because high voltage reduces upstream current, while local conversion limits the distance that very high low-voltage current must travel. AI accelerators have increased rack power demand and concentrated that demand into smaller spaces. Transporting very high power at 48 V or another low intermediate voltage requires large currents, heavier conductors, and more demanding connections.</p> 2718<p>An 800 VDC architecture carries a given amount of power at much lower current than a 48 V path. For example, ignoring conversion losses, 20 kW corresponds to about 25 A at 800 V but more than 416 A at 48 V. The lower upstream current can reduce distribution loss and conductor mass.</p> 2719<p>The difficult conversion does not disappear; it moves. A board located near the compute tray must step the high-voltage bus down efficiently while fitting within strict height, cooling, creepage, clearance, and service requirements. The architecture therefore trades a heavy low-voltage distribution path for a demanding high-ratio conversion stage closer to the load.</p> 2720<p>This is a developing architecture rather than a universal AI-server standard. Many current systems still use established AC-input PSUs, 48 V power shelves, or other intermediate-bus arrangements. An 800 VDC board should be described as a platform-specific solution, not as a required feature of every AI server.</p> 2721<h2>How Does an 800 V-to-6 V DC-DC Power Delivery Board Work?</h2> 2722<p>An 800 V-to-6 V board switches the high-voltage input, transfers energy through a high-ratio conversion stage, and delivers a regulated low-voltage, high-current output. Its exact topology belongs to the approved electrical design, but the functional path normally contains five recognizable sections.</p> 2723<p><strong><span style="color: #0070c0;">High-voltage input:</span></strong> Protection, filtering, controlled startup, and bus sensing prepare the incoming DC supply for conversion. High-voltage spacing and transient conditions affect both the schematic and the physical PCB.</p> 2724<p><strong><span style="color: #0070c0;">Switching stage:</span></strong> Power semiconductors switch the input at high frequency so energy can be transferred efficiently. Fast switching reduces the size of some magnetic components but makes parasitic inductance, gate-loop geometry, ringing, and EMI more important.</p> 2725<p><strong><span style="color: #0070c0;">Isolation and voltage transformation:</span></strong> Where isolation is required, high-frequency magnetics provide the safety barrier and most of the voltage transformation. The winding structure, insulation system, leakage inductance, and PCB connection geometry influence both loss and voltage stress.</p> 2726<p><strong><span style="color: #0070c0;">Secondary conversion:</span></strong> Low-voltage switching devices or synchronous rectifiers handle very high current. At this stage, milliohms matter. Copper paths, joints, terminals, and busbar interfaces can each become a meaningful heat source.</p> 2727<p><strong><span style="color: #0070c0;">Output distribution and control:</span></strong> Current sensing, voltage feedback, protection, current sharing, and communication support stable operation. The 6 V output may then feed additional point-of-load stages that produce the final processor rails.</p> 2728<p>The board is therefore not simply a thick-copper PCB. Electrical design, magnetics, switching behavior, insulation, thermal interfaces, and mechanical integration must work as one assembly.</p> 2729<h2>How Do Copper, Vias, and Busbars Carry High Current Without Excess Heat?</h2> 2730<p>Copper planes provide broad current paths, via arrays connect those paths through the stackup, and busbars carry current beyond practical PC
2730B-copper limits. They control heat only when the complete path has low resistance. Thicker copper cannot compensate for a narrow neck, insufficient via area, small connector contact, or resistive joint.</p> 2731<p><strong><span style="color: #0070c0;">Copper planes:</span></strong> Wide, short planes reduce resistance and spread heat. Heavy copper can increase current capacity, but it also affects etching, minimum spacing, laminate fill, board thickness, and copper balance.</p> 2732<p><strong><span style="color: #0070c0;">Parallel layers:</span></strong> Several copper layers can share current when the transitions between them are adequately connected. Current distribution is not automatically equal; entry points, via placement, geometry, and nearby magnetic fields influence which layers carry the greatest load.</p> 2733<p><strong><span style="color: #0070c0;">Via arrays:</span></strong> Vias move current between layers and conduct heat through the board. Their useful capacity depends on finished hole size, plating thickness, quantity, pitch, temperature rise, and how current enters the array. A large number of poorly positioned vias can still create local crowding.</p> 2734<p><strong><span style="color: #0070c0;">Busbars and terminals:</span></strong> Busbars can carry current with lower resistance and greater mechanical stiffness than PCB copper alone. The interface is often the critical area. Hole tolerances, surface flatness, fastener loading, plating, solder volume, and contact resistance affect the finished connection.</p> 2735<p><strong><span style="color: #0070c0;">Joints and component pads:</span></strong> Low-voltage output stages may use large leadless packages, clips, or high-current connectors. Voids, insufficient solder, uneven coplanarity, and localized copper imbalance can raise resistance and temperature even when the nominal PCB copper is adequate.</p> 2736<p>Thermal imaging and voltage-drop measurements are valuable because they reveal the complete path. A board can pass continuity testing and still contain a small resistive region that becomes visible only under load.</p> 2737<figure class="wp-block-image size-large wp-image-36673"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/ai-server-power-board-2.jpg" alt="AI server power board" width="1200" height="800" /></figure> 2738<h2>What Do GaN Power Stages Change in PCB Layout and Assembly?</h2> 2739<p>GaN power stages make loop inductance, gate routing, hidden solder joints, cleanliness, and thermal interfaces more critical. The devices can switch rapidly and reduce some switching losses, but their speed makes the physical interconnect part of the circuit behavior.</p> 2740<p>The switching loop must be compact because stray inductance can produce overshoot, ringing, EMI, and additional device stress. Gate-drive paths require controlled geometry and a short return path. Power and control grounds may need carefully managed connections so that high di/dt current does not disturb sensing or control signals.</p> 2741<p>Package style changes assembly requirements. Bottom-terminated GaN packages can hide solder joints from normal optical inspection. Pad geometry, stencil apertures, solder volume, placement accuracy, reflow profile, and void control influence both electrical and thermal performance. X-ray can examine hidden-joint coverage and major voiding where the package and acceptance criteria make that inspection meaningful.</p> 2742<p>Fast switching also increases the importance of cleanliness and spacing. Residue near high-field regions, damaged solder mask, copper-edge variation, and uncontrolled rework can reduce manufacturing margin. These issues are best managed through the released fabrication and assembly data rather than corrected after the board has already entered volume production.</p> 2743<p>GaN does not remove the need for magnetics, protection, thermal design, or validation. It changes where loss occurs and how sensitive the converter is to layout, assembly variation, and parasitic elements.</p> 2744<figure class="wp-block-image size-large wp-image-36674"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/ai-server-power-board-3.jpg" alt="AI server power board" width="1200" height="800" /></figure> 2745<h2>How Are Thermal Interfaces and Cooling Integrated Around the Board?</h2> 2746<p>Cooling is integrated by building a continuous thermal path from the power devices through the package, PCB or spreader, interface material, and heat sink or cold plate. Heat can also leave through copper planes, thermal vias, solder joints, busbars, and the PCB edge. The dominant path depends on the package and server cooling architecture.</p> 2747<p>Air-cooled assemblies may use heat sinks and directed airflow, but dense AI hardware increasingly places strict limits on airflow resistance and component height. C
2747onduction-cooled or liquid-cooled assemblies can move heat through a baseplate or cold plate, provided that the thermal interface remains flat, compressed, and electrically safe.</p> 2748<p><strong><span style="color: #0070c0;">A practical thermal stack can include:</span></strong></p> 2749<ul> 2750<li>the semiconductor junction and package.</li> 2751<li>solder or die-side thermal interface.</li> 2752<li>PCB copper and thermal vias.</li> 2753<li>a gap pad, phase-change material, or other interface material.</li> 2754<li>a heat spreader, heat sink, chassis, or liquid cold plate.</li> 2755</ul> 2756<p>Each interface adds thermal resistance. Excess bond-line thickness, board bow, uneven component height, voids, insufficient contact pressure, and tolerance accumulation can prevent the cooling hardware from performing as expected.</p> 2757<p>Mechanical and thermal design therefore affect PCB production. Copper balance influences flatness. Component height controls interface compression. Keep-out areas may be needed for cold-plate features and fasteners. Heavy magnetic parts and busbars may require additional support so that their mass does not strain solder joints during transport or service.</p> 2758<figure class="wp-block-image size-large wp-image-36675"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/ai-server-power-board-4.jpg" alt="AI server power board" width="1200" height="800" /></figure> 2759<h2>Which Board-Level Tests Reveal Loss, Temperature Rise, and Load-Step Problems?</h2> 2760<p>Efficiency testing reveals conversion loss, thermal measurements reveal hotspots, and load-step testing reveals transient response. Assembly inspection and preliminary electrical checks are still needed because those three performance tests do not identify every manufacturing defect.</p> 2761<figure class="wp-block-table"> 2762<table> 2763<tbody> 2764<tr> 2765<td><strong>Test</strong></td> 2766<td><strong>Primary finding</strong></td> 2767</tr> 2768<tr> 2769<td>AOI or visual inspection</td> 2770<td>Visible assembly defects</td> 2771</tr> 2772<tr> 2773<td>X-ray inspection</td> 2774<td>Hidden joints and major voiding</td> 2775</tr> 2776<tr> 2777<td>Continuity and resistance</td> 2778<td>Opens, shorts, and resistive paths</td> 2779</tr> 2780<tr> 2781<td>Controlled power-up</td> 2782<td>Startup and basic regulation</td> 2783</tr> 2784<tr> 2785<td>Efficiency measurement</td> 2786<td>Conversion loss</td> 2787</tr> 2788<tr> 2789<td>Thermal measurement</td> 2790<td>Local temperature rise</td> 2791</tr> 2792<tr> 2793<td>Load-step testing</td> 2794<td>Transient deviation and recovery</td> 2795</tr> 2796<tr> 2797<td>Insulation testing</td> 2798<td>Specified insulation integrity</td> 2799</tr> 2800</tbody> 2801</table> 2802</figure> 2803<p>Test conditions matter as much as the test name. Input voltage, load level, dwell time, airflow or cold-plate condition, sensor position, measurement bandwidth, and acceptance limits determine what the result means.</p> 2804<p>Board-level testing can verify the manufactured assembly against an agreed specification. Rack-level power sharing, accelerator workload transients, firmware interaction, system cooling, regulatory compliance, and field redundancy still require validation in the intended server platform.</p> 2805<figure class="wp-block-image size-large wp-image-36676"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/ai-server-power-board-5.jpg" alt="AI server power board" width="1200" height="800" /></figure> 2806<h2>How Can EBest Circuit Support High-Power DC-DC Board Production?</h2> 2807<p>EBest Circuit can turn a customer-approved high-power DC-DC design into a controlled PCB and PCBA production process. Support can extend from manufacturability review through fabrication, sourcing, assembly, inspection, and agreed board-level testing.</p> 2808<p><strong><span style="color: #0070c0;">Production support includes:</span></strong></p> 2809<ul> 2810<li>stackup, copper, spacing, hole, and copper-balance DFM.</li> 2811<li>multilayer and heavy-copper PCB fabrication.</li> 2812<li>controlled-BOM component sourcing.</li> 2813<li>power-device, magnetic-component, and connector assembly.</li> 2814<li>reflow, selective soldering, press-fit, and approved special processes.</li> 2815<li>AOI, X-ray, electrical inspection, cleanliness control, and traceability.</li> 2816<li>customer-defined fixtures and agreed board-level testing.</li> 2817</ul> 2818<p>High-voltage spacing, output-current paths, busbar interfaces, cooling surfaces, and test access deserve attention before release because they connect several manufacturing processes. A change that appears small in one file can affect PCB fabrication, stencil design, assembly order, fixture access, or final inspection.</p> 2819<p>EBest Circuit does not replace the customer’s power-topology, magnetics, firmware, mechanical, safety, or server-system engineering. Its role is to turn the released product definition into a controlled PCB and PCBA process, identify manufacturing conflicts, and provide agreed production evidence.</p> 2820<h2>AI Server Power Board FAQs</h2> 2821<p><strong>Is an AI server power board the same as a server motherboard?</strong></p> 2822<p>No. A server motherboard carries processors, memory, high-speed interfaces, management circuits, and local regulators. A power board is primarily responsible for defined power conversion or distribution. Some functions can share one assembly, but the terms are not interchangeable.</p> 2823<p><strong>Does every AI server use 800 VDC power delivery?</strong></p> 2824<p>
2824No. Many systems use AC-input PSUs, 48 V shelves, or other intermediate-bus architectures. The 800 VDC approach is an emerging option for reducing upstream current in very high-power systems, not a universal requirement.</p> 2825<p><strong>Why can a 6 V output still be difficult to manufacture?</strong></p> 2826<p>Low voltage at high power means very high current. Small resistance in copper transitions, solder joints, terminals, busbars, or connectors can create significant loss and heat. The board must control the complete current path, not only the nominal copper thickness.</p> 2827<p><strong>Are heavy-copper layers enough for a high-current power board?</strong></p> 2828<p>Not by themselves. Heavy copper helps reduce resistance, but via transitions, narrow geometries, connector contacts, component pads, busbar joints, and cooling interfaces may still limit the assembly.</p> 2829<p><strong>What information defines a manufacturable power board project?</strong></p> 2830<p>The released package normally includes PCB fabrication data, stackup and copper requirements, schematic, controlled BOM, assembly drawings, mechanical and cooling constraints, high-voltage requirements, and board-level test conditions. Together, these files define what must be built and how conformity will be evaluated.</p> 2831<p>EBest Circuit can review the manufacturing package for your <a href="https://www.bestpcbs.com/blog/2026/09/ai-server-power-board/">AI server power board</a> and support PCB fabrication, PCBA, inspection, and agreed testing. Send the released project files and production requirements to <strong>[email protected]</strong> to discuss the next build.</p> 2832 2833 </div> 2834 2835 2836 2837 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/ai-server-power-board/" rel="tag">AI server power board</a>, <a href="https://www.bestpcbs.com/blog/tag/ai-server-power-supply/" rel="tag">AI Server Power Supply</a>, <a href="https://www.bestpcbs.com/blog/tag/power-delivery-board/" rel="tag">Power Delivery Board</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/ai-pcb/" rel="category tag">AI PCB</a>, <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/bestpcb/" rel="category tag">bestpcb</a> | <span>Comments Closed</span></p> 2838 2839 </div> 2840 2841 2842 2843 2844 2845 2846 <div class="post-36933 post type-post status-publish format-standard hentry category-best-pcb category-bestpcb category-pcb-design tag-bga-escape-routing tag-bga-escape-routing-rules" id="post-36933"> 2847 2848 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/09/bga-escape-routing/" rel="bookmark" title="Permanent Link to BGA Escape Routing Rules and Methods: Fanout, Vias, and Layer Planning">BGA Escape Routing Rules and Methods: Fanout, Vias, and Layer Planning</a></h1> 2849 2850 <small>September 30th, 2026 <!-- by Jessica, Jessica --></small> 2851 2852 2853 2854 <div class="entry"> 2855 2856 <div class="yzp-no-index"></div> 2857<p><strong><a href="https://www.bestpcbs.com/blog/2026/09/bga-escape-routing/" title="">BGA escape routing</a></strong> moves signal, power, and ground connections from beneath a BGA package into usable PCB routing channels. The design is mainly controlled by <strong>BGA pitch, pad size, trace and spacing capability, via geometry, ball density, and PCB stackup</strong>. These constraints should be defined before detailed routing begins, especially for FPGAs, processors, SoCs, and memory devices.</p> 2858 2859 2860 2861<figure class="wp-block-image size-full is-resized"><a href="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing.jpg"><img loading="lazy" decoding="async" width="800" height="500" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing.jpg" alt="BGA Escape Routing, https://www.bestpcbs.com/blog/2026/09/bga-escape-routing/" class="wp-image-36935" style="width:700px" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing.jpg 800w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing-300x188.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-
2861Routing-768x480.jpg 768w" sizes="auto, (max-width: 800px) 100vw, 800px" /></a></figure> 2862 2863 2864 2865<h2 class="wp-block-heading">What Is BGA Escape Routing?</h2> 2866 2867 2868 2869<p><strong><a href="https://www.bestpcbs.com/blog/2026/09/bga-escape-routing/" title="">BGA escape routing</a></strong> is the process of bringing connections out of the BGA ball field so they can continue across the PCB. Outer ball rows can often escape directly on the component layer, while inner rows usually require vias to reach additional signal layers.</p> 2870 2871 2872 2873<p>BGA fanout is one part of this process. <strong>Fanout describes the transition from a BGA pad to a trace or via, while BGA escape routing covers the complete breakout from the ball field into open routing space.</strong> As the pitch decreases and the row count increases, routing channels become narrower and the via strategy becomes more critical.</p> 2874 2875 2876 2877<h2 class="wp-block-heading">What Design Constraints Define a BGA Escape Routing Strategy?</h2> 2878 2879 2880 2881<p>Before choosing a fanout method, check the package geometry and PCB fabrication limits together:</p> 2882 2883 2884 2885<ul class="wp-block-list"> 2886<li><strong>BGA pitch:</strong> Smaller pitch reduces the space available for traces and vias.</li> 2887 2888 2889 2890<li><strong>Pad diameter:</strong> Larger lands leave narrower routing channels.</li> 2891 2892 2893 2894<li><strong>Trace width and spacing:</strong> Determine how many traces can pass between pads.</li> 2895 2896 2897 2898<li><strong>Via geometry:</strong> Large via pads can block inner-row escape paths.</li> 2899 2900 2901 2902<li><strong>Via structure:</strong> Through-vias, blind vias, microvias, and via-in-pad structures provide different layer access.</li> 2903 2904 2905 2906<li><strong>PCB stackup:</strong> Defines the available routing layers and reference planes.</li> 2907 2908 2909 2910<li><strong>Fabrication limits:</strong> Set practical trace, spacing, drill, annular ring, and microvia rules.</li> 2911</ul> 2912 2913 2914 2915<p>These values cannot be optimized separately. A narrower trace does not solve the layout if the fanout vias still occupy the channel. <strong>Confirm the footprint, trace and spacing rules, via dimensions, and stackup before the BGA breakout is finalized.</strong></p> 2916 2917 2918 2919<h2 class="wp-block-heading">How Does BGA Pitch Affect the Escape Routing Method?</h2> 2920 2921 2922 2923<p>BGA pitch determines how much room is available between adjacent lands. Larger-pitch packages usually provide enough space for conventional dog-bone fanout and mechanically drilled vias. As the pitch decreases, via pads and trace clearances begin competing for the same space.</p> 2924 2925 2926 2927<figure class="wp-block-table"><table class="has-fixed-layout"><thead><tr><th><strong>BGA Pitch</strong></th><th><strong>
2927Typical Approach</strong></th><th><strong>Main Constraint</strong></th></tr></thead><tbody><tr><td>1.27 mm</td><td>Dog-bone and through-via</td><td>Usually generous routing space</td></tr><tr><td>1.0 mm</td><td>Dog-bone and through-via</td><td>Via and trace clearance</td></tr><tr><td>0.8 mm</td><td>Optimized dog-bone or smaller via</td><td>Fewer routing channels</td></tr><tr><td>0.65 mm</td><td>Small via, HDI, or via-in-pad</td><td>Inner-row access</td></tr><tr><td>0.5 mm and below</td><td>Microvia and via-in-pad often considered</td><td>Very limited breakout space</td></tr></tbody></table></figure> 2928 2929 2930 2931<p>These are planning ranges rather than fixed rules. A simple 0.8 mm package may route with standard through-vias, while a dense FPGA at the same pitch may not. <strong>Ball count, number of rows, signal assignment, trace and spacing rules, and available routing layers matter as much as pitch.</strong></p> 2932 2933 2934 2935<h2 class="wp-block-heading">How Do You Determine Whether Traces Can Pass Between BGA Pads?</h2> 2936 2937 2938 2939<p>Start with the physical space between adjacent PCB lands. If the ball pitch is P and the land diameter is D:</p> 2940 2941 2942 2943<p><strong>Available pad gap = P – D</strong></p> 2944 2945 2946 2947<p>For one trace to pass through that gap, the <strong>trace width plus twice the required clearance must fit within the available pad gap</strong>.</p> 2948 2949 2950 2951<p>If two traces must share the same channel, the required trace-to-trace spacing must also be included. This simple check quickly shows whether the intended breakout is realistic before the full BGA fanout is created.</p> 2952 2953 2954 2955<p>The calculation is only a starting point. Copper thickness, etching tolerance, registration, and actual fabrication capability reduce the usable margin. <strong>A trace that fits mathematically is not automatically a reliable production rule.</strong> Avoid designing every channel at the minimum trace and spacing limit unless the routing density requires it.</p> 2956 2957 2958 2959<h2 class="wp-block-heading">How Do You Route the Outer Rows of a BGA?</h2> 2960 2961 2962 2963<p>Outer rows normally provide the easiest paths out of the package. The goal is to use that advantage without blocking the deeper rows.</p> 2964 2965 2966 2967<ul class="wp-block-list"> 2968<li><strong>Route directly outward where possible:</strong> Avoid unnecessary vias when a connection can remain on the component layer.</li> 2969 2970 2971 2972<li><strong>Preserve inner routing channels:</strong> Do not fill valuable space with easy outer-row connections before the deeper rows are planned.</li> 2973 2974 2975 2976<li><strong>Escape toward the destination:</strong> Route toward nearby memory, connectors, processors, or other ICs when placement is already defined.</li> 2977 2978 2979 2980<li><strong>Keep sensitive nets short:</strong> Avoid unnecessary width changes and layer transitions.</li> 2981</ul> 2982 2983 2984 2985<p>Direct routing is useful, but it should still follow the complete BGA escape routing plan. <strong>The easiest connection should not occupy the only practical path available to a more constrained signal.</strong></p> 2986 2987 2988 2989<h2 class="wp-block-heading">How Do You Escape the Inner Rows of a BGA?</h2> 2990 2991 2992 2993<p>Inner rows are blocked by surrounding balls, so most of their connections must transition to another layer before leaving the package area.</p> 2994 2995 2996 2997<p>A practical sequence is:</p> 2998 2999 3000 3001<ul class="wp-block-list"> 3002<li><strong>Plan the deepest rows first:</strong> Reserve their escape channels before easier signals use the available space.</li> 3003 3004 3005 3006<li><strong>Move signals to internal layers:</strong> Use through-vias, blind vias, or microvias where appropriate.</li> 3007 3008 3009 3010<li><strong>Assign layers by routing capacity:</strong> Do not rely on a fixed one-row-per-layer assumption.</li> 3011 3012 3013 3014<li><strong>Reserve space for power and ground vias:</strong> These connections also consume breakout area.</li> 3015 3016 3017 3018<li><strong>Change the via strategy when necessary:</strong> If conventional via pads occupy too much space, consider via-in-pad or microvias.</li> 3019</ul> 3020 3021 3022 3023<p>There is no universal rule that a certain number of BGA rows requires a fixed number of PCB layers. <strong>The required layer count depends on the actual pad, via, and trace geometry.</strong></p> 3024 3025 3026 3027<figure class="wp-block-image size-full is-resized"><a href="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-
3027Routing-21.png"><img loading="lazy" decoding="async" width="768" height="512" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing-21.png" alt="BGA Escape Routing, https://www.bestpcbs.com/blog/2026/09/bga-escape-routing/" class="wp-image-36937" style="width:700px" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing-21.png 768w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing-21-300x200.png 300w" sizes="auto, (max-width: 768px) 100vw, 768px" /></a></figure> 3028 3029 3030 3031<h2 class="wp-block-heading">When Should You Use Dog-Bone Fanout for BGA Escape Routing?</h2> 3032 3033 3034 3035<p>Dog-bone fanout connects a BGA land to a nearby via with a short trace. It works well when the pitch provides enough room for the connection and the via pad does not block the channels required by surrounding signals.</p> 3036 3037 3038 3039<p>This method is common with larger-pitch packages and many 1.0 mm or 0.8 mm BGAs because conventional drilled vias can often be used without pushing the PCB process to aggressive limits. It also keeps the via outside the solder land, simplifying fabrication compared with via-in-pad.</p> 3040 3041 3042 3043<p>The limitation appears when the via field becomes denser than the available routing channels. <strong>Once conventional fanout vias begin blocking the paths required by deeper rows, via-in-pad or microvias are usually more effective than continuing to shrink the dog-bone geometry.</strong></p> 3044 3045 3046 3047<h2 class="wp-block-heading">When Should You Use Via-in-Pad for BGA Escape Routing?</h2> 3048 3049 3050 3051<p>Via-in-pad becomes useful when a conventional fanout via occupies too much space beside the BGA land or prevents access to deeper rows. Placing the via directly in the land frees routing space between adjacent pads and allows an immediate layer transition.</p> 3052 3053 3054 3055<p>This approach is common in fine-pitch FPGA, processor, SoC, memory, and other high-density BGA layouts. It can also shorten the pad-to-via transition for high-speed signals.</p> 3056 3057 3058 3059<p>The via normally needs to be filled and planarized for BGA assembly. <strong>An open via inside the solder land can draw solder into the hole during reflow and reduce the solder volume at the joint.</strong> Via-in-pad therefore adds fabrication steps, but it is justified when it solves a real routing-density or signal-transition problem.</p> 3060 3061 3062 3063<h2 class="wp-block-heading">When Are Microvias Needed for Fine-Pitch BGA Escape Routing?</h2> 3064 3065 3066 3067<p>Microvias are used when conventional mechanically drilled vias occupy too much area. Their smaller geometry allows signals to move between nearby PCB layers while leaving more routing space for other connections.</p> 3068 3069 3070 3071<p>They are especially useful in HDI BGA escape routing where via-in-pad is combined with blind microvias. Instead of carrying a large through-via through the entire stackup, a signal can transition only to the layer where it needs to be routed.</p> 3072 3073 3074 3075<p>Microvias may be stacked or staggered depending on the layer structure and routing density. <strong>Their use should be driven by routing requirements rather than BGA pitch alone.</strong> If conventional vias still provide enough escape space, adding microvias only increases fabrication complexity.</p> 3076 3077 3078 3079<figure class="wp-block-image size-full"><a href="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing-31.png"><img loading="lazy" decoding="async" width="768" height="512" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing-31.png" alt="BGA Escape Routing, https://www.bestpcbs.com/blog/2026/09/bga-escape-routing/" class="wp-image-36938" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing-31.png 768w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/BGA-Escape-Routing-31-300x200.png 300w" sizes="auto, (max-width: 768px) 100vw, 768px" /></a></figure> 3080 3081 3082 3083<h2 class="wp-block-heading">How Many PCB Layers Do You Need for BGA Escape Routing?</h2> 3084 3085 3086 3087<p>Layer count depends on how many signals must leave the BGA and how much routing capacity each layer provides. Pitch alone cannot determine the required stackup.</p> 3088 3089 3090 3091<p>A dense device may require more routing layers because of <strong>high ball count, limited trace channels, power and ground planes, controlled-impedance nets, differential pairs, and high-speed interfaces</strong>. Outer signals may remain on the component layer, while deeper rows move to different internal layers.</p> 3092 3093 3094 3095<p>DDR, PCIe, USB, Ethernet, MIPI, and SerDes connections may also require specific reference planes, so their layer allocation cannot be based only on available routing space.</p> 3096 3097 3098 3099<p><strong>Use enough layers to complete the breakout without forcing the entire BGA area to minimum fabrication rules.</strong> In some designs, one additional signal layer provides better production margin than aggressive trace and via reduction across several layers.</p> 3100 3101 3102 3103<h2 class="wp-block-heading">How Should You Escape Differential Pairs From a BGA?</h2> 3104 3105 3106 3107<p>Differential pairs should leave the BGA with similar geometry on both sides of the pair. Their breakout length, via type, antipad geometry, and reference environment should remain as consistent as the package allows.</p> 3108 3109 3110 3111<p>If a layer transition is required, both members should normally use equivalent vias and share the same reference structure. Avoid giving one side an extra via or a significantly longer escape path.</p> 3112 3113 3114 3115<p>Detailed length tuning is better performed once the pair reaches open board space. <strong>Inside the BGA field, maintaining pair symmetry and a clean return path is more useful than forcing exact length matching with unnecessary meanders.</strong></p> 3116 3117 3118 3119<p>For PCIe, USB, Ethernet, MIPI, and SerDes interfaces, the breakout should be planned together with <strong>controlled impedance, reference-plane continuity, and via transition design</strong>.</p> 3120 3121 3122 3123<h2 class="wp-block-heading">How Should Power and Ground Balls Be Handled During BGA Escape Routing?</h2> 3124 3125 3126 3127<p>Power and ground connections should be planned at the same time as the signal fanout. Leaving them until the end can create a breakout that works for signals but performs poorly for power delivery.</p> 3128 3129 3130 3131<p>Power balls should have short connections to their planes, with enough via capacity for the expected current. Ground vias should also be available near high-speed signal transitions so the return current can follow a short path when a signal changes reference layers.</p> 3132 3133 3134 3135<p>Decoupling capacitors affect the same area. Their connections should remain short and direct rather than being forced around an already congested fanout. <strong>Signal escape, power delivery, ground return, and decoupling placement should be treated as one routing problem.</strong></p> 3136 3137 3138 3139<h2 class="wp-block-heading">What BGA Escape Routing Mistakes Should You Avoid?</h2> 3140 3141 3142 3143<p>Most BGA breakout problems result from using the available space in the wrong order or choosing geometry before checking the complete routing path.</p> 3144 3145 3146 3147<ul class="wp-block-list"> 3148<li><strong>Oversized fanout vias:</strong> Block channels required by deeper rows.</li> 3149 3150 3151 3152<li><strong>Unsupported trace and spacing rules:</strong> Create DFM problems or reduce production margin.</li> 3153 3154 3155 3156<li><strong>Routing easy nets first:</strong> Can trap inner-row signals.</li> 3157 3158 3159 3160<li><strong>Open via-in-pad:</strong> Can draw solder away from the BGA joint.</li> 3161 3162 3163 3164<li><strong>Late stackup definition:</strong> Forces routing and reference-plane changes later.</li> 3165 3166 3167 3168<li><strong>Too many layer transitions:</strong> Add vias and high-speed discontinuities.</li> 3169 3170 3171 3172<li><strong>Broken return paths:</strong> Increase signal integrity and EMI risk.</li> 3173 3174 3175 3176<li><strong>Poor differential symmetry:</strong> Introduces unnecessary skew.</li> 3177 3178 3179 3180<li><strong>Blocked power access:</strong> Leaves insufficient room for power and ground vias.</li> 3181 3182 3183 3184<li><strong>Minimum rules everywhere:</strong> Makes production less tolerant of normal process variation.</li> 3185</ul> 3186 3187 3188 3189<p><strong>Solve the most constrained areas first, then use the remaining channels for less difficult connections.</strong></p> 3190 3191 3192 3193<h2 class="wp-block-heading">What Should You Verify Before Releasing a BGA PCB for Fabrication?</h2> 3194 3195 3196 3197<p>Passing PCB DRC is not enough. The completed BGA escape routing should also match the intended fabrication and assembly process.</p> 3198 3199 3200 3201<ul class="wp-block-list"> 3202<li><strong>BGA footprint:</strong> Verify pitch, pad diameter, orientation, and solder mask geometry.</li> 3203 3204 3205 3206<li><strong>Trace and spacing:</strong> Check the smallest neck-down and copper clearance.</li> 3207 3208 3209 3210<li><strong>Via geometry:</strong> Verify drill diameter, pad size, annular ring, antipad, and layer span.</li> 3211 3212 3213 3214<li><strong>Via-in-pad:</strong> Confirm filling, plating, and planarization requirements.</li> 3215 3216 3217 3218<li><strong>Microvias:</strong> Verify the layer span and stacked or staggered construction.</li> 3219 3220 3221 3222<li><strong>
3222PCB stackup:</strong> Check routing layers, dielectric thickness, and reference planes.</li> 3223 3224 3225 3226<li><strong>High-speed nets:</strong> Verify impedance, differential symmetry, and return paths.</li> 3227 3228 3229 3230<li><strong>Power delivery:</strong> Check plane access, via quantity, and decoupling paths.</li> 3231 3232 3233 3234<li><strong>Manufacturing margin:</strong> Maintain sufficient tolerance beyond absolute process limits.</li> 3235</ul> 3236 3237 3238 3239<p>For HDI, fine-pitch BGA, via-in-pad, and microvia designs, <strong>a DFM review before fabrication can identify breakout and stackup conflicts before they reach production.</strong></p> 3240 3241 3242 3243<h2 class="wp-block-heading">FAQs About BGA Escape Routing</h2> 3244 3245 3246 3247<p><strong>Q1: Can FPGA pin swapping make BGA routing easier?</strong></p> 3248 3249 3250 3251<p><strong>A1:</strong> Yes, when the FPGA architecture allows it. Reassigning compatible I/O pins can reduce trace crossings and improve escape direction. <strong>Pin changes must still respect I/O banks, voltage domains, differential-pair assignments, clock-capable pins, and device-specific restrictions.</strong></p> 3252 3253 3254 3255<p><strong>Q2: Should unused or NC BGA balls still have PCB pads?</strong></p> 3256 3257 3258 3259<p><strong>A2:</strong> Usually yes. Follow the recommended land pattern unless the component documentation allows a change. Removing an NC pad only to create more routing space may affect assembly or future device compatibility. <strong>Do not alter the footprint without package-specific guidance.</strong></p> 3260 3261 3262 3263<p><strong>Q3: Does copper thickness affect BGA breakout capability?</strong></p> 3264 3265 3266 3267<p><strong>A3:</strong> Yes. Heavier copper generally requires more allowance during etching, making very fine trace and spacing geometry harder to produce. <strong>Copper thickness should be considered when setting routing rules beneath a dense BGA.</strong></p> 3268 3269 3270 3271<p><strong>Q4: Does solder mask design matter around BGA pads?</strong></p> 3272 3273 3274 3275<p><strong>A4:</strong> Yes. Solder mask registration and pad definition affect the usable area around each land. The mask design should support reliable assembly while maintaining realistic fabrication tolerance. <strong>Do not reduce mask clearances only to gain routing space.</strong></p> 3276 3277 3278 3279<p><strong>Q5: Can BGA escape traces use a local neck-down?</strong></p> 3280 3281 3282 3283<p><strong>A5:</strong> Yes. A short neck-down can help a trace pass through a restricted breakout channel and then return to its normal width outside the BGA. <strong>Keep the narrow section short and check its impedance or current-carrying requirements where relevant.</strong></p> 3284 3285 3286 3287<p><strong>Q6: Should test points be placed inside the BGA breakout area?</strong></p> 3288 3289 3290 3291<p><strong>A6:</strong> Usually not unless the available space clearly supports them. Test pads consume routing space and can increase congestion around already constrained signals. <strong>Place test access outside the dense ball field whenever practical.</strong></p> 3292 3293 3294 3295<p><strong>Q7: Can thermal vias interfere with BGA routing?</strong></p> 3296 3297 3298 3299<p><strong>A7:</strong> Yes. Thermal vias near the package can occupy channels required by signals, power, or ground connections. <strong>Plan thermal management and BGA routing together so thermal structures do not block critical breakout paths.</strong></p> 3300 3301 3302 3303<p><strong>Q8: Does BGA breakout affect EMI performance?</strong></p> 3304 3305 3306 3307<p><strong>A8:</strong> It can. Long escape paths, poor reference continuity, unnecessary layer changes, and large return loops can increase unwanted radiation. <strong>Short routes and continuous return paths help reduce EMI risk around high-speed BGA interfaces.</strong></p> 3308 3309 3310 3311<p><strong>Q9: Can buried vias reduce congestion around a BGA?</strong></p> 3312 3313 3314 3315<p><strong>A9:</strong> Yes. Buried vias connect internal layers without occupying every layer in the PCB stackup, which can free routing space elsewhere. They also increase fabrication complexity, so <strong>use them only when the routing benefit justifies the additional process steps.</strong></p> 3316 3317 3318 3319<p><strong>Q10: How does nearby component placement affect BGA routing?</strong></p> 3320 3321 3322 3323<p><strong>A10:</strong> Placement determines where major signal groups should leave the package. Memory, connectors, decoupling capacitors, and adjacent ICs should be positioned
3323so related nets can escape in useful directions. <strong>Good placement can reduce crossings, vias, and unnecessary routing length.</strong></p> 3324 3325 3326 3327<p><strong>Q11: Can BGA congestion be reduced before routing begins?</strong></p> 3328 3329 3330 3331<p><strong>A11:</strong> Yes. Review the pin map, interface direction, component placement, stackup, and signal grouping before detailed fanout. Programmable devices may also allow legal pin reassignment. <strong>Early planning is usually more effective than repairing blocked routes later.</strong></p> 3332 3333 3334 3335<p><strong>Q12: Does dense BGA routing make rework harder?</strong></p> 3336 3337 3338 3339<p><strong>A12:</strong> It can. Fine pitch, via-in-pad, dense neighboring components, and limited access can all increase rework difficulty. <strong>Adequate component clearance and stable pad and via construction help reduce rework risk.</strong></p> 3340 3341 3342 3343<h2 class="wp-block-heading">Conclusion</h2> 3344 3345 3346 3347<p>Effective BGA escape routing depends on <strong>available routing space, via geometry, and PCB stackup</strong>. Plan the inner rows first, use conventional fanout where it fits, and move to via-in-pad or microvias when routing density requires them.</p> 3348 3349 3350 3351<p>For fine-pitch BGA, HDI, via-in-pad, microvia, or high-layer-count PCB projects, EBest Circuit can review your <strong>Gerber files, stackup, BGA pitch, via structure, and impedance requirements</strong> before production. Contact <strong><a href="mailto:[email protected]">[email protected]</a></strong> for technical review and quotation.</p> 3352 3353 </div> 3354 3355 3356 3357 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/bga-escape-routing/" rel="tag">BGA Escape Routing</a>, <a href="https://www.bestpcbs.com/blog/tag/bga-escape-routing-rules/" rel="tag">BGA Escape Routing Rules</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/bestpcb/" rel="category tag">bestpcb</a>, <a href="https://www.bestpcbs.com/blog/category/pcb-design/" rel="category tag">PCB Design</a> | <a href="https://www.bestpcbs.com/blog/2026/09/bga-escape-routing/#respond">No Comments »</a></p> 3358 3359 </div> 3360 3361 3362 3363 3364 3365 3366 <div class="post-36879 post type-post status-publish format-standard hentry category-best-pcb category-bestpcb category-pcba tag-bga-soldering tag-head-in-pillow-defect tag-smt-assembly" id="post-36879"> 3367 3368 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/09/head-in-pillow-defect/" rel="bookmark" title="Permanent Link to Why Does a Head-in-Pillow Defect Occur in BGA Soldering?">Why Does a Head-in-Pillow Defect Occur in BGA Soldering?</a></h1> 3369 3370 <small>September 29th, 2026 <!-- by zeng, liuyan --></small> 3371 3372 3373 3374 <div class="entry"> 3375 3376 <div class="yzp-no-index"></div> 3377<p>A <a href="https://www.bestpcbs.com/blog/2026/09/head-in-pillow-defect/">head-in-pillow defect</a> occurs when a BGA solder ball and the printed solder paste fail to join properly during reflow. The two solder masses may touch, allowing the board to pass an electrical test, while the joint remains mechanically weak. This makes HIP especially troublesome in assemblies that work initially but develop intermittent connections during handling, temperature changes, or service.</p> 3378 3379 3380 3381<p>EBest Circuit (Best Technology) supports BGA assembly with <a href="https://www.bestpcbs.com/blog/2025/12/solder-paste-inspection/">solder paste inspection</a>, reflow soldering, and X-ray inspection. These capabilities help connect hidden solder-joint problems with the printing and assembly processes that influence them. For a BGA build affected by recurring soldering defects, contact <strong>[email protected]</strong> to discuss the assembly process and inspection approach.</p> 3382 3383 3384 3385<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" width="1200" height="800" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect1.jpg" alt="head-in-pillow defect" class="wp-image-36876" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect1.jpg 1200w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect1-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect1-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect1-768x512.jpg 768w" sizes="auto, (max-width: 1200px) 100v
3385w, 1200px" /><figcaption class="wp-element-caption">Illustration of a head-in-pillow joint: the solder ball contacts the reflowed solder without forming a continuous metallurgical joint.</figcaption></figure> 3386 3387 3388 3389<h2 class="wp-block-heading">What Is a Head-in-Pillow Defect?</h2> 3390 3391 3392 3393<p>A head-in-pillow defect is an incompletely joined interface between the component's solder ball and the reflowed solder paste on the PCB. The paste may have wetted the copper land correctly, yet failed to merge with the ball above it. In a section through the joint, the ball can resemble a head resting on a pillow of solder.</p> 3394 3395 3396 3397<p><strong>Physical contact does not establish a sound solder joint.</strong> A reliable connection requires the solder surfaces to wet and coalesce. If an oxide film or other wetting barrier remains between them, the contact can conduct electricity without providing the strength expected from a properly formed joint.</p> 3398 3399 3400 3401<p>The resulting failure may be an immediate open circuit or an intermittent connection. Temperature changes or mechanical movement can disturb that contact and expose the weakness. However, these symptoms alone do not identify HIP: cracked joints, damaged pads, and other BGA defects can produce similar behavior.</p> 3402 3403 3404 3405<h2 class="wp-block-heading">What Causes a Head in Pillow Defect During Reflow?</h2> 3406 3407 3408 3409<p>HIP develops when the solder ball and paste fail to maintain or recover the contact and wetting conditions needed to merge. Dynamic warpage is one important trigger, but oxidation, contamination, paste behavior, and flux activity also influence the outcome.</p> 3410 3411 3412 3413<p><strong><span style="color:#0070c0">A typical warpage-related sequence is:</span></strong></p> 3414 3415 3416 3417<ol class="wp-block-list"> 3418<li> <strong>Initial contact:</strong> Placement brings the BGA balls into contact with the printed paste deposits.</li> 3419 3420 3421<li> <strong>Temporary separation:</strong> As the assembly heats, the package or PCB changes shape. Some balls lift away from their deposits.</li> 3422 3423 3424<li> <strong>Separate reflow and oxidation:</strong> The paste reflows on the land while the separated surfaces remain exposed. Oxide films can interfere with subsequent wetting.</li> 3425 3426 3427<li> <strong>Incomplete reunion:</strong> The package moves back toward the board, but renewed contact does not produce full coalescence if the interface is no longer wettable or the solder has solidified.</li> 3428</ol> 3429 3430 3431 3432<p>This explains why a package that appears flat after cooling can still contain defective joints. Its final shape does not reveal how it moved while the solder was forming.</p> 3433 3434 3435 3436<p>Warpage is not the only route to HIP. Oxidized or contaminated solder balls can resist wetting even when their initial contact with the paste is adequate. Flux must remove surface oxides and protect the interface during the useful soldering period; the presence of flux residue after reflow does not prove that sufficient activity remained when the ball and paste needed to join.</p> 3437 3438 3439 3440<p>Defects concentrated near BGA corners can suggest package movement or temperature differences. That pattern is a diagnostic clue, not proof of a single cause.</p> 3441 3442 3443 3444<h2 class="wp-block-heading">How Does a Head on Pillow Defect Differ from a Non-Wet Open?</h2> 3445 3446 3447 3448<p>Head on pillow, also called HoP, describes the same general defect family as head-in-pillow. The important distinction from a BGA non-wet open is <strong>where the connection fails to form</strong>.</p> 3449 3450 3451 3452<figure class="wp-block-table"><table class="has-fixed-layout"><thead><tr><th>Feature</th><th>Head-in-pillow / head on pillow</th><th>BGA non-wet open</th></tr></thead><tbody><tr><td>Main failed interface</td><td>Between the solder ball and reflowed paste</td><td>Between the solder and PCB land</td></tr><tr><td>Typical solder distribution</td><td>Separate solder masses remain on the component and board sides</td><td>Paste can join the component ball and pull away from the land</td></tr><tr><td>Main diagnostic question</td><td>Did the ball and paste coalesce?</td><td>Did the solder wet the PCB land?</td></tr></tbody></table></figure> 3453 3454 3455 3456<p>In the non-wet-open mechanism described here, solder can accumulate on the component side while the PCB land remains unwetted. HIP can leave solder attached to the land, with the defective interface above it.</p> 3457 3458 3459 3460<p>Both conditions may produce an open or unstable electrical connection, but they direct the investigation toward different interfaces. A dark line, unusual ball shape, or failed continuity test cannot establish that distinction by itself. Examination of the affected joint must locate the actual separation or wetting failure.</p> 3461 3462 3463 3464<h2 class="wp-block-heading">Why Can a Head-in-Pillow Defect Escape Inspection?</h2> 3465 3466 3467 3468<p>HIP can escape inspection because the failed interface is hidden and may still make electrical contact. Different inspection methods reveal different parts of that problem.</p> 3469 3470 3471 3472<p><strong>Visual inspection and AOI have limited access.</strong> Most BGA joints sit beneath the package. AOI can identify placement errors and visible assembly defects, but it cannot establish the integrity of every hidden ball-to-paste interface.</p> 3473 3474 3475 3476<p><strong>Electrical testing captures the connection under the test conditions.</strong> A weak interface may touch well enough to pass continuity or functional testing. If the contact changes with temperature or movement later, the failure appears after the test has finished. Passing once therefore does not demonstrate that the solder masses have formed a reliable joint.</p> 3477 3478 3479 3480<p><strong>X-ray images require careful interpretation.</strong> A top-down image projects the joint through its thickness, so two touching but incompletely joined solder masses can overlap in the image. Oblique views or suitable three-dimensional imaging may reveal separation or unusual joint geometry more clearly. However, a narrow waist or suspicious outline is not, by itself, proof of HIP; joint shape can also create misleading indications.</p> 3481 3482 3483 3484<p>When electrical symptoms and X-ray findings disagree, further failure analysis may be needed. Cross-sectioning or a controlled dye-and-pry investigation can provide additional evidence, although these methods are destructive and depend on preparation and interpretation. Such analysis is most useful when it targets the suspected location and is correlated with the original failure.</p> 3485 3486 3487 3488<p>Inspection can identify suspect joints and support diagnosis. Preventing their formation still depends on controlling the assembly process.</p> 3489 3490 3491 3492<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" width="1200" height="800" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect3.jpg" alt="head-in-pillow defect" class="wp-image-36878" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect3.jpg 1200w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect3-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect3-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect3-768x512.jpg 768w" sizes="auto, (max-width: 1200px) 100v
3492w, 1200px" /><figcaption class="wp-element-caption">Illustrative BGA X-ray inspection scene. A two-dimensional projection alone may not resolve an unfused head-in-pillow interface.</figcaption></figure> 3493 3494 3495 3496<h2 class="wp-block-heading">How Do Solder Paste and Stencil Printing Affect HIP Risk?</h2> 3497 3498 3499 3500<p>Solder paste affects HIP through both <strong>contact geometry and wetting behavior</strong>. The printed deposit must reach the ball consistently, while the flux must remain effective during joint formation.</p> 3501 3502 3503 3504<p>A low or uneven deposit can leave less contact margin when a package moves during reflow. Deposit height matters alongside volume: paste that spreads or slumps can contain solder but provide less vertical contact with the ball. Printing offset can also reduce the contact area between the ball and its intended deposit.</p> 3505 3506 3507 3508<p>SPI helps reveal insufficient deposits, height variation, and printing misalignment before placement. Comparing the affected BGA locations with their print measurements can show whether the defect follows a printing problem. Consistent deposits at failing locations, however, leave package movement and wetting behavior as important possibilities.</p> 3509 3510 3511 3512<p>Increasing stencil aperture size is not a universal correction. Additional paste may improve contact in a particular process, but too much can introduce bridging or alter joint geometry. The useful adjustment is one that improves deposit consistency and contact without creating another defect.</p> 3513 3514 3515 3516<p>Flux chemistry also matters. Paste behavior during heating, oxide removal, and protection against further oxidation influence whether separated surfaces can join again. A paste that prints well at room temperature may still need evaluation under the actual BGA reflow conditions. HIP reduction therefore requires both a suitable material and a repeatable printing process.</p> 3517 3518 3519 3520<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" width="1200" height="800" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect2.jpg" alt="head-in-pillow defect" class="wp-image-36877" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect2.jpg 1200w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect2-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect2-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/head-in-pillow-defect2-768x512.jpg 768w" sizes="auto, (max-width: 1200px) 100vw, 1200px" /><figcaption class="wp-element-caption">Illustrative inspection scene showing solder paste deposits on a BGA land pattern before component placement.</figcaption></figure> 3521 3522 3523 3524<h2 class="wp-block-heading">Can a Hotter Reflow Profile Eliminate HIP?</h2> 3525 3526 3527 3528<p>No. A hotter profile can help when inadequate heating is the problem, but it can also increase warpage, oxidation, or flux depletion. Temperature alone cannot ensure that the ball and paste remain in contact and wet each other.</p> 3529 3530 3531 3532<p>The relevant temperature is the one experienced by the assembly, not simply the oven setpoint. A large BGA and the surrounding PCB can heat unevenly. Raising the oven temperature to correct a colder location may expose another part of the assembly to excessive heat.</p> 3533 3534 3535 3536<p>The timing matters as well. Solder must reach the required reflow conditions while enough flux activity remains to support wetting. A prolonged heating cycle may consume that activity before difficult interfaces have joined. A profile that is too short or too cool can leave inadequate wetting or reflow at the coldest joints.</p> 3537 3538 3539 3540<p>Useful profiling therefore considers temperature differences across the package, peak temperatures, and time above the relevant alloy's liquidus. Thermocouple measurements at representative locations help show how the assembly actually heats. The acceptable window must also respect the solder paste guidance and component temperature limits.</p> 3541 3542 3543 3544<p>If the underlying problem is severe package movement or a poorly wettable ball surface, profile changes alone may not resolve it. Paste, component condition, and thermal behavior have to be considered together.</p> 3545 3546 3547 3548<h2 class="wp-block-heading">Can a Head-in-Pillow Defect Be Repaired?</h2> 3549 3550 3551 3552<p>An assembly affected by HIP can often be recovered through controlled BGA rework, provided the PCB lands and surrounding structure remain suitable for repair. Simply reheating the package until the board works again does not establish that the defective interface has been corrected.</p> 3553 3554 3555 3556<p>Rework may involve removing the affected component, preparing the PCB lands, applying fresh solder paste, and attaching an appropriate replacement device under a characterized thermal profile. Removal and replacement both need controlled heating to avoid pad damage, excessive board deformation, or package damage.</p> 3557 3558 3559 3560<p>Component reuse depends on the device supplier's restrictions and the condition of the removed part. Reballing is not automatically necessary or permitted, and it cannot repair damage inside a component or beneath a PCB land.</p> 3561 3562 3563 3564<p>If the original failure still needs investigation, relevant observations should be preserved before rework changes the joint. After repair, inspection and electrical verification must address the repaired site and the original symptom. A successful repair also needs the cause of the first failure addressed; otherwise, the replacement process can reproduce the same defect.</p> 3565 3566 3567 3568<h2 class="wp-block-heading">How Can EBest Circuit Help Reduce HIP Risk?</h2> 3569 3570 3571 3572<p>EBest Circuit supports HIP risk reduction through BGA assembly, solder paste inspection, reflow process control, and X-ray inspection of hidden joints. The value comes from connecting these stages: a soldering problem found after reflow can be compared with the paste deposits and assembly conditions that preceded it.</p> 3573 3574 3575 3576<p><strong><span style="color:#0070c0">The relevant capabilities include:</span></strong></p> 3577 3578 3579 3580<ul class="wp-block-list"> 3581<li><strong>SPI:</strong> Identifies paste deposition problems that can reduce consistent ball-to-paste contact.</li> 3582 3583 3584<li><strong>BGA placement and reflow soldering:</strong> Support accurate assembly and thermal processing matched to the board and component requirements.</li> 3585 3586 3587<li><strong>Air and nitrogen reflow capability:</strong> Allows the atmosphere to be considered alongside paste and profile requirements where oxidation is a concern.</li> 3588 3589 3590<li><strong>X-ray inspection:</strong> Provides information about hidden joint geometry and helps identify locations needing further investigation.</li> 3591</ul> 3592 3593 3594 3595<p>For a new BGA build, these controls help address soldering conditions before production expands. For a recurring defect, they help narrow whether printing, thermal behavior, or the soldering interface needs attention. Ambiguous inspection findings may still require further analysis before the failure mechanism is established.</p> 3596 3597 3598 3599<p>The assembly approach should fit the affected package and board. A generic hotter profile or larger stencil aperture cannot replace that process understanding.</p> 3600 3601 3602 3603<h2 class="wp-block-heading">FAQs About Head-in-Pillow Defect</h2> 3604 3605 3606 3607<p><strong>1. Are HIP and HoP different defects?</strong></p> 3608 3609 3610 3611<p>HIP usually means head-in-pillow, while HoP means head on pillow. Both commonly describe incomplete joining between a component's solder ball and reflowed paste. Terminology can vary, so the failed interface is more useful than the abbreviation when discussing a diagnosis.</p> 3612 3613 3614 3615<p><strong>2. Does HIP occur only with lead-free solder?</strong></p> 3616 3617 3618 3619<p>No. HIP is strongly associated with lead-free BGA assembly, but the underlying problem is incomplete wetting and coalescence. Using a tin-lead process does not by itself guarantee that the ball and paste will form a sound joint.</p> 3620 3621 3622 3623<p><strong>3. Can nitrogen reflow completely prevent HIP?</strong></p> 3624 3625 3626 3627<p>No. Nitrogen can reduce oxidation during reflow, but it does not remove package warpage, correct an insufficient paste deposit, or guarantee wetting of an already contaminated surface. It is one process variable, not a complete prevention method.</p> 3628 3629 3630 3631<p><strong>4. Will adding more solder paste solve the problem?</strong></p> 3632 3633 3634 3635<p>Only when inadequate deposition or contact is a contributing cause and the change remains suitable for the joint geometry. More paste cannot reliably compensate for poor solderability or excessive package movement, and excessive deposits can create bridging.</p> 3636 3637 3638 3639<p><strong>5. Is a solder void the same as a head-in-pillow defect?</strong></p> 3640 3641 3642 3643<p>No. A void is a cavity within the solder. HIP is a failure of the ball and paste to join properly at their interface. Both can occur in BGA assemblies, but they require different interpretation and corrective action.</p> 3644 3645 3646 3647<p>
3647For help reducing <a href="https://www.bestpcbs.com/blog/2026/09/head-in-pillow-defect/">head-in-pillow defect</a> risk in your next BGA assembly, contact <strong>[email protected]</strong>. EBest Circuit can discuss the printing, reflow, and inspection approach for your board, including how to investigate recurring hidden-joint failures.</p> 3648 3649 </div> 3650 3651 3652 3653 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/bga-soldering/" rel="tag">BGA soldering</a>, <a href="https://www.bestpcbs.com/blog/tag/head-in-pillow-defect/" rel="tag">head-in-pillow defect</a>, <a href="https://www.bestpcbs.com/blog/tag/smt-assembly/" rel="tag">SMT assembly</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/bestpcb/" rel="category tag">bestpcb</a>, <a href="https://www.bestpcbs.com/blog/category/pcba/" rel="category tag">PCBA</a> | <a href="https://www.bestpcbs.com/blog/2026/09/head-in-pillow-defect/#respond">No Comments »</a></p> 3654 3655 </div> 3656 3657 3658 3659 3660 3661 3662 <div class="post-36866 post type-post status-publish format-standard hentry category-best-pcb category-bestpcb category-design-guide tag-circuit-diagram tag-circuit-protection tag-fuse-symbol" id="post-36866"> 3663 3664 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/09/fuse-symbol/" rel="bookmark" title="Permanent Link to How to Read a Fuse Symbol on a Circuit Diagram">How to Read a Fuse Symbol on a Circuit Diagram</a></h1> 3665 3666 <small>September 29th, 2026 <!-- by zeng, liuyan --></small> 3667 3668 3669 3670 <div class="entry"> 3671 3672 <div class="yzp-no-index"></div> 3673<p>A <strong><a href="https://www.bestpcbs.com/blog/2026/09/fuse-symbol/">fuse symbol</a></strong> marks a protective device that opens a circuit when excessive current melts its fuse element. Reading it correctly involves more than recognizing the shape: the nearby reference number, rating, and circuit connections explain which fuse it is and what it protects.</p> 3674<p>At EBest Circuit, we support PCB fabrication, component sourcing, and SMT or through-hole assembly from your approved design. Matching the specified fuse to its PCB footprint and assembly documentation helps prevent component mismatches during production. For PCB and PCBA project support, contact <strong>[email protected]</strong>.</p> 3675<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-1.jpg" alt="fuse symbol" class="wp-image-36862" width="1500" height="1000" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-1.jpg 1500w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-1-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-1-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-1-768x512.jpg 768w" sizes="auto, (max-width: 1500px) 100vw, 1500px" /></figure> 3676<h2>What Does a Fuse Symbol Look Like?</h2> 3677<p><strong>A common fuse symbol is a small rectangle with a straight line running through its center.</strong> Another familiar form uses a short curved or S-shaped element between the connecting wires. Both represent a fuse rather than its physical package.</p> 3678<p>The rectangle can resemble an IEC resistor symbol. The useful distinction is that the common rectangular fuse symbol has a line through the box, while the basic rectangular resistor symbol does not. Nearby identifiers also help: <strong>F1</strong> commonly identifies a fuse; <strong>R1</strong> identifies a resistor.</p> 3679<p>A curved fuse element can also resemble other symbols in a small drawing. Read the graphic together with its identifier and the drawing legend, rather than relying on the outline alone.</p> 3680<h2>Why Do Fuse Symbols Look Different Across Diagrams?</h2> 3681<p><strong>Drawing standards, symbol libraries, and the amount of detail shown can all change a fuse’s appearance.</strong> IEC 60617 and IEEE/ANSI conventions are common references, but their implementations can overlap.</p> 3682<figure class="wp-block-table"> 3683<table> 3684<thead> 3685<tr> 3686<th>Difference in the drawing</th> 3687<th>What it means</th> 3688</tr> 3689</thead> 3690<tbody> 3691<tr> 3692<td>Rectangle with a center line or a curved element</td> 3693<td>Alternative representations encountered in different drawing conventions</td> 3694</tr> 3695<tr> 3696<td>Horizontal or vertical orientation</td> 3697<td>The symbol has been rotated to fit the circuit layout</td> 3698</tr> 3699<tr> 3700<td>Added striker or alarm-contact detail</td> 3701<td>The fuse assembly includes an indication or actuation feature</td> 3702</tr> 3703</tbody> 3704</table> 3705</figure> 3706<p><strong>A rectangle alone does not establish whether the entire drawing follows IEC or IEEE conventions.</strong> Both IEC and IEEE symbol libraries can contain the rectangular center-line form. Likewise, a different symbol shape does not automatically mean a different current rating or operating speed.</p> 3707<h2>What Do the Markings Beside a Fuse Symbol Mean?</h2> 3708<p><strong>The <a href="https://www.bestpcbs.com/blog/2026/07/circuit-board-markings-how-to-read-pcb-symbols-codes/">reference designator</a> identifies the component; the specification describes its electrical characteristics.</strong> For example, <strong>F1</strong> means a particular fuse in the design, not a 1-amp fuse.</p> 3709<p><strong style="color:#0070c0;">Consider a fuse identified as <strong>F1</strong>, with the specification <strong>T3.15AL250V</strong>. In the miniature-fuse marking convention used for this example:</strong></p> 3710<figure class="wp-block-table"> 3711<table> 3712<thead> 3713<tr> 3714<th>Marking</th> 3715<th>Meaning</th> 3716</tr> 3717</thead> 3718<tbody> 3719<tr> 3720<td>F1</td> 3721<td>Component reference, used to connect the schematic, BOM, and assembly drawing</td> 3722</tr> 3723<tr> 3724<td>T</td> 3725<td>Time-delay characteristic</td> 3726</tr> 3727<tr> 3728<td>3.15A</td> 3729<td>Rated current of 3.15 amperes</td> 3730</tr> 3731<tr> 3732<td>L</td> 3733<td>Low breaking-capacity category</td> 3734</tr> 3735<tr> 3736<td>250V</td> 3737<td>Rated voltage of 250 volts</td> 3738</tr> 3739</tbody> 3740</table> 3741</figure> 3742<p>The rated current and breaking capacity describe different things. <strong>Rated current concerns normal current carrying; breaking capacity concerns safely interrupting a fault current.</strong> The letter L does not provide the complete numerical interrupting rating.</p> 3743<p>Similarly, 250V is not a voltage at which the fuse automatically blows. The applicable AC or DC rating comes from the device specification. This marking format is not universal for all fuse packages, particularly small surface-mount parts with manufacturer-specific codes.</p> 3744<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-2.jpg" alt="fuse symbol" class="wp-image-36864" width="1500" height="1000" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-2.jpg 1500w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-2-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-2-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-2-768x512.jpg 768w" sizes="auto, (max-width: 1500px) 100v
3744w, 1500px" /></figure> 3745<h2>How Are Fast-Blow and Slow-Blow Fuses Identified on Schematics?</h2> 3746<p><strong>The basic fuse symbol often stays the same; the accompanying value, note, or part number identifies the operating characteristic.</strong> In common miniature-fuse markings, F indicates fast-acting and T indicates time-delay.</p> 3747<ul> 3748<li><strong style="color:#0070c0;">Fast-blow fuse:</strong> Intended to interrupt overcurrent without the intentional surge tolerance of a time-delay design. It still takes time to operate.</li> 3749<li><strong style="color:#0070c0;">Slow-blow fuse:</strong> Designed to withstand specified brief current surges, such as those associated with startup, while providing overcurrent protection.</li> 3750</ul> 3751<p>For example, <strong>F2A</strong> and <strong>T2A</strong> both indicate a 2A current rating in this marking system, but their time-current behavior differs. They should not be treated as interchangeable solely because the current rating matches.</p> 3752<p>Also distinguish the <strong>F in F1</strong>, which identifies the component, from the <strong>F in F2A</strong>, which describes its speed. The manufacturer’s time-current curve defines the response more precisely than either the symbol or the word âfast.â</p> 3753<h2>How Do You Read a Fuse Circuit Diagram?</h2> 3754<p><strong>Follow the current path through the fuse to the load and back to the supply.</strong> A fuse protecting a branch is connected in series with that branch, so the branch current passes through its element.</p> 3755<p><strong style="color:#0070c0;">For a simple 12V DC circuit, the path is:</strong></p> 3756<p><strong>Supply +12V â F1 â Load â Supply return (0V)</strong></p> 3757<p><strong style="color:#0070c0;">This example shows three useful relationships:</strong></p> 3758<ol> 3759<li><strong style="color:#0070c0;">Normal operation:</strong> F1 conducts the load current and completes the supply path.</li> 3760<li><strong style="color:#0070c0;">Downstream fault:</strong> A short circuit can increase the current through F1. Whether and how quickly it opens depends on the available fault current and fuse characteristics.</li> 3761<li><strong style="color:#0070c0;">After F1 opens:</strong> The load loses this supply path. The section between the source and F1 can remain energized.</li> 3762</ol> 3763<p>If another branch connects to the supply before F1, that branch is outside F1’s protection path. This is why the connection points matter more than how close the fuse appears to a component on the page.</p> 3764<h2>How Does a Fuse Symbol Relate to the Actual Component?</h2> 3765<p><strong>One basic schematic symbol can represent several physical fuse packages.</strong> It may correspond to a small SMD chip, a leaded fuse, or a cartridge fitted into a holder.</p> 3766<figure class="wp-block-table"> 3767<table> 3768<thead> 3769<tr> 3770<th>Design element</th> 3771<th>What it describes</th> 3772</tr> 3773</thead> 3774<tbody> 3775<tr> 3776<td>Schematic symbol</td> 3777<td>Electrical function and circuit connections</td> 3778</tr> 3779<tr> 3780<td><a href="https://www.bestpcbs.com/blog/2026/09/pcb-bom-management/">BOM part number</a></td> 3781<td>The specified device and its characteristics</td> 3782</tr> 3783<tr> 3784<td>PCB footprint</td> 3785<td>Pads or holes needed for the mounted component</td> 3786</tr> 3787<tr> 3788<td>Assembly reference</td> 3789<td>Where that component belongs on the board</td> 3790</tr> 3791</tbody> 3792</table> 3793</figure> 3794<p>For a cartridge fuse, the PCB may carry the <strong>holder</strong>, while the replaceable fuse sits inside it. The board footprint must therefore match the holder’s terminals and dimensions.</p> 3795<p>Changing to another fuse with the same current rating may still require a different footprint, holder, or assembly process. The symbol alone does not establish mechanical compatibility.</p> 3796<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-3.jpg" alt="fuse symbol" class="wp-image-36865" width="1500" height="1000" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-3.jpg 1500w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-3-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-3-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/fuse-symbol-3-768x512.jpg 768w" sizes="auto, (max-width: 1500px) 100v
3796w, 1500px" /></figure> 3797<h2>Does a Fuse Symbol Show Whether the Fuse Has Blown?</h2> 3798<p><strong>An ordinary schematic fuse symbol does not report the fuse’s present condition.</strong> It identifies the device and its connection in the intended circuit.</p> 3799<p>A fault-analysis drawing may explicitly show an open fuse, while another drawing may include a fuse-operated alarm contact. Those details need to be interpreted through the drawing notes or legend; they are not live status indications by themselves.</p> 3800<p>The physical fuse’s condition requires inspection or measurement. For a conventional fuse, continuity testing is performed with power disconnected and stored energy discharged. Parallel circuit paths can produce a misleading reading, so isolation may be necessary. A printed symbol or an intact-looking fuse body is not sufficient evidence that the fuse is working.</p> 3801<h2>FAQs About Fuse Symbols</h2> 3802<p><strong>Do AC and DC fuses use different symbols?</strong></p> 3803<p>The basic symbol can be the same. AC and DC suitability is established by the specified fuse’s ratings, not by its symbol alone. An AC voltage rating does not automatically establish an equivalent DC rating.</p> 3804<p><strong>How is a thermal fuse different from an ordinary fuse?</strong></p> 3805<p>A thermal fuse opens at a specified temperature, while an ordinary overcurrent fuse responds to heating caused by current through its element. Thermal-fuse drawings may include a temperature notation or a distinct library symbol. Its electrical ratings still matter.</p> 3806<p><strong>Is a resettable PTC the same as a fuse?</strong></p> 3807<p>No. A resettable PTC increases its resistance when it trips, limiting current rather than creating the permanent open circuit of a melted fuse element. It can recover after the fault is removed and it cools, subject to the device’s operating conditions.</p> 3808<p><strong>Does an SMD fuse need a special schematic symbol?</strong></p> 3809<p>Usually, the basic fuse symbol is sufficient. The BOM and footprint distinguish an SMD package from a leaded or cartridge version. A tiny code printed on the component may be a manufacturer-specific rating code.</p> 3810<p><strong>Are car fuse-box icons the same as schematic fuse symbols?</strong></p> 3811<p>Not necessarily. A fuse-box cover may use icons to identify the protected function, such as lighting or a power outlet. A schematic fuse symbol identifies the protective device within the electrical circuit. The vehicle’s legend explains its particular icons.</p> 3812<p>For a PCB assembly project, the <strong><a href="https://www.bestpcbs.com/blog/2026/09/fuse-symbol/">fuse symbol</a></strong>, specified part, and physical footprint should describe the same intended device. EBest Circuit can support fabrication, sourcing, and assembly from your approved files. Discuss your next build with us at <strong>[email protected]</strong>.</p> 3813 3814 </div> 3815 3816 3817 3818 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/circuit-diagram/" rel="tag">Circuit Diagram</a>, <a href="https://www.bestpcbs.com/blog/tag/circuit-protection/" rel="tag">Circuit Protection</a>, <a href="https://www.bestpcbs.com/blog/tag/fuse-symbol/" rel="tag">fuse symbol</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/bestpcb/" rel="category tag">bestpcb</a>, <a href="https://www.bestpcbs.com/blog/category/design-guide/" rel="category tag">Design Guide</a> | <a href="https://www.bestpcbs.com/blog/2026/09/fuse-symbol/#respond">No Comments »</a></p> 3819 3820 </div> 3821 3822 3823 3824 3825 3826 3827 <div class="post-36860 post type-post status-publish format-standard hentry category-best-pcb category-bestpcb category-electronic-components tag-ntc-thermistor tag-ptc-thermistor tag-thermistor-symbol" id="post-36860"> 3828 3829 <h1 class="_title"><a href="https://www.bestpcbs.com/blog/2026/09/thermistor-symbol/" rel="bookmark" title="Permanent Link to Thermistor Symbol Explained: Identify NTC and PTC">Thermistor Symbol Explained: Identify NTC and PTC</a></h1> 3830 3831 <small>September 29th, 2026 <!-- by zeng, liuyan --></small> 3832 3833 3834 3835 <div class="entry"> 3836 3837 <div class="yzp-no-index"></div> 3838<p>A <a href="https://www.bestpcbs.com/blog/2026/09/thermistor-symbol/">thermistor symbol</a> represents a resistor whose resistance changes with temperature. Recognizing it helps you understand whether a circuit monitors heat, compensates for temperature changes, or limits current. The basic shape identifies a temperature-dependent resistor, while nearby labels and the component specification explain whether it is an NTC or PTC device.</p> 3839<p>EBest Circuit (Best Technology) supports PCB fabrication, component sourcing, and assembly for temperature-monitoring, control, and power electronics. Bringing these stages together helps carry the specified thermistor and its mounting requirements from the BOM into the assembled board. For a PCB or PCBA project using thermistors, contact <strong>[email protected]</strong>.</p> 3840<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-1.jpg" alt="thermistor symbol" class="wp-image-36857" width="1200" height="800" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-1.jpg 1200w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-1-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-1-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-1-768x512.jpg 768w" sizes="auto, (max-width: 1200px) 100v
3840w, 1200px" /></figure> 3841<h2>What Does a Thermistor Symbol Look Like?</h2> 3842<p>A common thermistor symbol combines a resistor body with a diagonal temperature-dependence mark. The resistor may appear as a rectangle or a zigzag, depending on the drawing convention. Many rectangular versions use a diagonal stroke with a short bent end; some drawings add a temperature notation such as t or θ.</p> 3843<p>The distinguishing feature is the temperature-related mark added to the resistor. A plain rectangle or zigzag alone normally represents an ordinary resistor. The outline can therefore vary without changing the component’s basic function.</p> 3844<p>A schematic symbol describes electrical behavior rather than physical appearance. A small surface-mount chip, a coated bead, and a leaded disc can all be thermistors, even though their circuit symbols look similar. Likewise, a thermistor drawn beside an IC may actually be mounted elsewhere on the PCB or connected through a cable.</p> 3845<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-2.jpg" alt="thermistor symbol" class="wp-image-36858" width="1200" height="800" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-2.jpg 1200w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-2-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-2-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-2-768x512.jpg 768w" sizes="auto, (max-width: 1200px) 100vw, 1200px" /></figure> 3846<h2>NTC Thermistor Symbol vs. PTC Thermistor Symbol</h2> 3847<p>NTC and PTC describe opposite directions of resistance change. <strong>An NTC thermistor decreases in resistance as its temperature rises; a PTC thermistor increases in resistance over its specified operating region.</strong></p> 3848<table> 3849<thead> 3850<tr> 3851<th>Type</th> 3852<th>Meaning</th> 3853<th>Resistance as temperature rises</th> 3854<th>Possible schematic identification</th> 3855</tr> 3856</thead> 3857<tbody> 3858<tr> 3859<td>NTC</td> 3860<td>Negative temperature coefficient</td> 3861<td>Decreases</td> 3862<td>NTC label or a negative temperature-coefficient notation</td> 3863</tr> 3864<tr> 3865<td>PTC</td> 3866<td>Positive temperature coefficient</td> 3867<td>Increases</td> 3868<td>PTC label or a positive temperature-coefficient notation</td> 3869</tr> 3870</tbody> 3871</table> 3872<p>Some schematics use the same generic thermistor symbol for both types. In that case, the part number or accompanying component description identifies the behavior. The angle of the diagonal line alone is not a reliable way to distinguish NTC from PTC.</p> 3873<p>A plus or minus sign used to describe the temperature coefficient refers to the direction of resistance change. It does not identify positive and negative terminals.</p> 3874<p>The distinction matters when reading a circuit. Replacing an NTC sensing element with a PTC device would reverse the resistance response to heat. Even within one type, components can have different resistance curves: two NTC thermistors with the same room-temperature resistance are not necessarily interchangeable across the operating temperature range.</p> 3875<h2>Thermistor vs. Variable Resistor and LDR Symbols</h2> 3876<p>These symbols all build on a resistor shape, but their added marks identify different causes of resistance change. The most useful distinction is temperature, adjustment, or light.</p> 3877<table> 3878<thead> 3879<tr> 3880<th>Component</th> 3881<th>Common visual clue</th> 3882<th>What changes the resistance?</th> 3883</tr> 3884</thead> 3885<tbody> 3886<tr> 3887<td>Thermistor</td> 3888<td>Temperature-dependence stroke, sometimes with a temperature notation</td> 3889<td>The thermistor’s temperature</td> 3890</tr> 3891<tr> 3892<td>Variable resistor</td> 3893<td>An arrow crossing or pointing to the resistor body</td> 3894<td>Adjustment of a movable contact</td> 3895</tr> 3896<tr> 3897<td>Potentiometer</td> 3898<td>A wiper connection leading to the resistor, usually with three terminals</td> 3899<td>Wiper position</td> 3900</tr> 3901<tr> 3902<td>LDR or photoresistor</td> 3903<td>Arrows pointing toward the resistor, sometimes inside a circle</td> 3904<td>Incident light</td> 3905</tr> 3906</tbody> 3907</table> 3908<p>A thermistor’s diagonal mark can resemble the line through a variable resistor at a glance. The arrowhead and wiper connection are useful clues for an adjustable resistor. On an LDR, the incoming arrows represent light rather than electrical terminals.</p> 3909<p>For example, a variable resistor in a temperature-control circuit may set the temperature threshold, while a nearby thermistor senses temperature. They can affect the same control function but perform different jobs. Treating both as adjustable resistors would obscure how the circuit responds to heat.</p> 3910<h2>What Do the Numbers Beside a Thermistor Symbol Mean?</h2> 3911<p>Numbers near the symbol usually describe resistance or identify the component. They do not, by themselves, state the temperature being measured.</p> 3912<p><strong>A 10 kΩ rating specifies resistance at a reference temperature.</strong> If an NTC is marked R25 = 10 kΩ, its nominal resistance is 10,000 ohms at 25°C. It will have a different resistance at other temperatures. A bare â10Kâ label gives less information, so its reference temperature comes from the component specification.</p> 3913<p><strong>A tolerance applies to a defined parameter.</strong> A rating such as R25 = 10 kΩ ±1% describes the permitted resistance variation at 25°C. It does not mean that the assembled circuit measures temperature to ±1°C or ±1%.</p> 3914<p><strong>The B value describes an NTC’s resistanceâtemperature characteristic.</strong> A notation such as B25/85 identifies a beta value determined using 25°C and 85°C. It is expressed in kelvins. A larger B value generally indicates a steeper resistance change for the same nominal resistance over the relevant range; it is not a maximum operating temperature.</p> 3915<p>These distinctions explain why a replacement marked â10K NTCâ may produce a different temperature reading. Matching the nominal resistance alone does not match the complete resistance curve. The sensing circuit’s conversion method must correspond to the fitted thermistor’s characteristics.</p> 3916<h2>How Does a Thermistor Work in a Temperature-Sensing Circuit?</h2> 3917<p>A thermistor often forms a voltage divider with a fixed resistor. As temperature changes its resistance, the divider produces a changing voltage that an ADC or comparator can read.</p> 3918<p>
3918Consider a fixed resistor connected from a 3.3 V supply to a sensing node, with an NTC connected from that node to ground. For an ideal divider with negligible input loading:</p> 3919<p><strong>Vout = Vsupply à RNTC / (Rfixed + RNTC)</strong></p> 3920<p>If both resistances are 10 kΩ, the node voltage is 1.65 V. If heating reduces the NTC resistance to 5 kΩ, the voltage becomes 1.10 V. These are illustrative resistance values; the temperature corresponding to 5 kΩ depends on the particular thermistor.</p> 3921<p>With this arrangement, heating lowers the output voltage. If the NTC and fixed resistor exchange positions, heating raises the output voltage instead. The same NTC behavior can therefore produce either voltage direction, depending on where it sits in the divider.</p> 3922<p>The controller converts the voltage into resistance and then into temperature using an appropriate resistanceâtemperature table or model. Because an NTC’s response is nonlinear, a fixed number of ADC counts does not generally represent the same temperature change across the full range.</p> 3923<p>The thermistor also dissipates power when current flows through it. Excessive sensing current can warm the component and shift its reading above the temperature it is intended to measure. Thermal placement matters for the same reason: a thermistor close to a power resistor may respond strongly to that local heat source, even when the surrounding air is cooler.</p> 3924<figure class="wp-block-image size-full"><img loading="lazy" decoding="async" src="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-3.jpg" alt="thermistor symbol" class="wp-image-36859" width="1200" height="800" srcset="https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-3.jpg 1200w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-3-300x200.jpg 300w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-3-1024x683.jpg 1024w, https://www.bestpcbs.com/blog/wp-content/uploads/2026/09/thermistor-symbol-3-768x512.jpg 768w" sizes="auto, (max-width: 1200px) 100vw, 1200px" /></figure> 3925<h2>Thermistor Uses in Temperature Sensing and Circuit Protection</h2> 3926<p>Thermistors can measure temperature or use their own heating to influence current. The application depends on the component’s construction and ratings, not just the symbol on the schematic.</p> 3927<p><strong>Temperature sensing and control.</strong> NTC thermistors commonly provide temperature feedback in battery packs, power supplies, HVAC equipment, and electronic assemblies. Their changing resistance can support fan control, charging limits, or an overtemperature response. Thermal contact determines what is being sensed: a device attached to a battery cell responds differently from one exposed to air on the PCB.</p> 3928<p><strong>Inrush current limiting.</strong> A power NTC placed in series with a supply has a relatively high resistance when cold. This reduces the initial charging current into capacitors. As current heats the NTC, its resistance falls, reducing its voltage drop during operation. A rapid restart while the device is still hot can provide less inrush limiting because it has not recovered its cold resistance.</p> 3929<p><strong>Overcurrent protection.</strong> A PTC intended for protection heats as current flows. Its rising resistance limits current, and suitable switching types show a pronounced increase near their transition region. Recovery depen
3929ds on the device cooling and on the conditions in the surrounding circuit. This behavior differs from a fuse that opens permanently.</p> 3930<p>A small NTC temperature sensor is not a substitute for a power-rated inrush limiter. Similarly, a PTC temperature-sensing device is not automatically suitable as a resettable protector. The symbol identifies a temperature-dependent resistance; the component specification establishes which of these jobs it can perform.</p> 3931<h2>FAQs About Thermistor Symbol</h2> 3932<p><strong>Does a thermistor have polarity?</strong></p> 3933<p>A conventional two-terminal thermistor is non-polarized. Reversing its two leads does not reverse its resistanceâtemperature behavior. A sensor module containing additional electronics may have supply and signal connections that must be connected in the specified direction.</p> 3934<p><strong>What do TH and RT mean beside a thermistor symbol?</strong></p> 3935<p>They may be reference-designator prefixes used to identify thermistors in a particular schematic. Naming conventions vary between projects and CAD libraries. A designator such as TH1 identifies a component instance; its value and part number provide the electrical details.</p> 3936<p><strong>Does the symbol tell you whether the thermistor is surface-mount or through-hole?</strong></p> 3937<p>No. The same electrical symbol can be associated with different packages. The assigned <a href="https://www.bestpcbs.com/blog/2025/11/unlock-the-secrets-of-footprint-pcb-for-fast-turn-pcb-fabrication/">footprint</a> and part number identify the physical device, including its pads or leads and mounting dimensions.</p> 3938<p><strong>Is a thermistor the same as a thermocouple?</strong></p> 3939<p>No. A thermistor changes resistance with temperature and needs an electrical measurement circuit. A thermocouple produces a small voltage related to the temperature difference between its sensing and reference junctions. They use different symbols and measurement methods.</p> 3940<p><strong>How can you identify NTC or PTC when the schematic only shows a generic symbol?</strong></p> 3941<p>The part number and its resistanceâtemperature data provide the clearest answer. For a suitable isolated component, measuring resistance at two known temperatures can indicate the direction of change. An in-circuit reading may include parallel paths, so it can misrepresent the thermistor’s resistance.</p> 3942<p>Once a <a href="https://www.bestpcbs.com/blog/2026/09/thermistor-symbol/">thermistor symbol</a> is linked to the correct component and circuit function, that specification needs to carry through into the physical assembly. EBest Circuit supports PCB fabrication and PCBA for thermistor-based monitoring and control boards, including component sourcing and assembly to the approved design. Contact <strong>[email protected]</strong> to discuss prototype or production assembly for your board.</p> 3943 3944 </div> 3945 3946 3947 3948 <p class="postmetadata">Tags: <a href="https://www.bestpcbs.com/blog/tag/ntc-thermistor/" rel="tag">NTC Thermistor</a>, <a href="https://www.bestpcbs.com/blog/tag/ptc-thermistor/" rel="tag">PTC Thermistor</a>, <a href="https://www.bestpcbs.com/blog/tag/thermistor-symbol/" rel="tag">Thermistor Symbol</a><br /> Posted in <a href="https://www.bestpcbs.com/blog/category/best-pcb/" rel="category tag">best pcb</a>, <a href="https://www.bestpcbs.com/blog/category/bestpcb/" rel="category tag">bestpcb</a>, <a href="https://www.bestpcbs.com/blog/category/electronic-components/" rel="category tag">Electronic Components</a> | <a href="https://www.bestpcbs.com/blog/2026/09/thermistor-symbol/#respond">No Comments »</a></p> 3949 3950 </div> 3951 3952 3953 3954 3955 3956 3957 <div class="navigation"> 3958 3959 <div class="alignleft"><a href="https://www.bestpcbs.com/blog/page/2/" >« Older Entries</a></div> 3960 3961 <div class="alignright"></div> 3962 3963 </div> 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 </article> 3975 3976 3977 3978<aside id="sidebar"> 3979 3980 3981<div class="metal-domes-item-quote"> 3982 3983 3984 3985 3986 3987 <div class="metal-domes-photo"> 3988 3989 3990 <img src="https://www.bestpcbs.com/blog/wp-content/themes/default/2024/images/0.jpg" alt="PCB & PCBA MANUFACTURING" /> 3991 3992 3993 </div> 3994 3995 3996 <h4> PCB & PCBA MANUFACTURING</h4> 3997 3998 3999 4000 4001 4002 <ul> 4003 4004 4005 <li>TURNKEY SERVICE</li> 4006 4007 4008 <li>20 YRS EXPERIENCE </li> 4009 4010 4011 <li>HIGH QUALITY, ON-TIME DELIVERY</li> 4012 4013 4014 </ul> 4015 4016 4017 <a href="https://www.bestpcbs.com/contact/index.htm" class="metal-domes-btn_quotenow"><i class="icon-envelop"></i> QUOTE NOW</a> 4018 4019 4020 <div class="_pic"> 4021 4022 4023 <img src="https://www.bestpcbs.com/blog/wp-content/themes/default/2024/images/1.png" alt="PCB & PCBA MANUFACTURING" /> 4024 4025 4026 </div> 4027 4028 4029 </div> 4030 4031 4032 4033 4034 4035<div class="metal-domes-module-search"> </div> 4036 4037 4038 <div class="sidebarBox"> 4039 4040 4041 4042 4043 4044 <h3 class="metal-domes-title-sidebar"><span>Recent Posts</span></h3> 4045 4046 4047 4048 4049 4050 <ul class="metal-domes-list-news2"> 4051 4052 4053 <li> 4054 4055 4056 <a href="https://www.bestpcbs.com/manufacturing/pcb-manufacturing.htm">PCB Manufacturing Process<time>Feb-09th-2020 </time></a> 4057 4058 4059 </li> 4060 4061 4062 <li> 4063 4064 4065 <a href="https://www.bestpcbs.com/manufacturing/thick-film-ceramic-pcb-manufacturing-process.htm">
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These cookies ensure basic functionalities and security features of the website, anonymously. 4489<table class="wt-cli-element cookielawinfo-row-cat-table cookielawinfo-winter"><thead><tr><th scope="col" class="cookielawinfo-column-1">Cookie</th><th scope="col" class="cookielawinfo-column-3">Duration</th><th scope="col" class="cookielawinfo-column-4">Description</th></tr></thead><tbody><tr class="cookielawinfo-row"><td class="cookielawinfo-column-1">cookielawinfo-checkbox-analytics</td><td class="cookielawinfo-column-3">11 months</td><td class="cookielawinfo-column-4">This cookie is set by GDPR Cookie Consent plugin. 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4624<script type="text/javascript" id="rocket-preload-links-js-after"> 4625/* <![CDATA[ */ 4626(function() { 4627"use strict";var r="function"==typeof Symbol&&"symbol"==typeof Symbol.iterator?function(e){return typeof e}:function(e){return e&&"function"==typeof Symbol&&e.constructor===Symbol&&e!==Symbol.prototype?"symbol":typeof e},e=function(){function i(e,t){for(var n=0;n<t.length;n++){var i=t[n];i.enumerable=i.enumerable||!1,i.configurable=!0,"value"in i&&(i.writable=!0),Object.defineProperty(e,i.key,i)}}return function(e,t,n){return t&&i(e.prototype,t),n&&i(e,n),e}}();function i(e,t){if(!(e instanceof t))throw new TypeError("Cannot call a class as a function")}var t=function(){function n(e,t){i(this,n),this.browser=e,this.config=t,this.options=this.browser.options,this.prefetched=new Set,this.eventTime=null,this.threshold=1111,this.numOnHover=0}return e(n,[{key:"init",value:function(){!this.browser.supportsLinkPrefetch()||this.browser.isDataSaverModeOn()||this.browser.isSlowConnection()||(this.regex={excludeUris:RegExp(this.config.excludeUris,"i"),images:RegExp(".("+this.config.imageExt+")$","i"),fileExt:RegExp(".("+this.config.fileExt+")$","i")},this._initListeners(this))}},{key:"_initListeners",value:function(e){-1<this.config.onHoverDelay&&document.addEventListener("mouseover",e.listener.bind(e),e.listenerOptions),document.addEventListener("mousedown",e.listener.bind(e),e.listenerOptions),document.addEventListener("touchstart",e.listener.bind(e),e.listenerOptions)}},{key:"listener",value:function(e){var t=e.target.closest("a"),n=this._prepareUrl(t);if(null!==n)switch(e.type){case"mousedown":case"touchstart":this._addPrefetchLink(n);break;case"mouseover":this._earlyPrefetch(t,n,"mouseout")}}},{key:"_earlyPrefetch",value:function(t,e,n){var i=this,r=setTimeout(function(){if(r=null,0===i.numOnHover)setTimeout(function(){return i.numOnHover=0},1e3);else if(i.numOnHover>i.config.rateThrottle)return;i.numOnHover++,i._addPrefetchLink(e)},this.config.onHoverDelay);t.addEventListener(n,function e(){t.removeEventListener(n,e,{passive:!0}),null!==r&&(clearTimeout(r),r=null)},{passive:!0})}},{key:"_addPrefetchLink",value:function(i){return this.prefetched.add(i.href),new Promise(function(e,t){var n=document.createElement("link");n.rel="prefetch",n.href=i.href,n.onload=e,n.onerror=t,document.head.appendChild(n)}).catch(function(){})}},{key:"_prepareUrl",value:function(e){if(null===e||"object"!==(void 0===e?"undefined":r(e))||!1 in e||-1===["http:","https:"].indexOf(e.protocol))return null;var t=e.href.substring(0,this.config.siteUrl.length),n=this._getPathname(e.href,t),i={original:e.href,protocol:e.protocol,origin:t,pathname:n,href:t+n};return this._isLinkOk(i)?i:null}},{key:"_getPathname",value:function(e,t){var n=t?e.substring(this.config.siteUrl.length):e;return n.startsWith("/")||(n="/"+n),this._shouldAddTrailingSlash(n)?n+"/":n}},{key:"_shouldAddTrailingSlash",value:function(e){return this.config.usesTrailingSlash&&!e.endsWith("/")&&!this.regex.fileExt.test(e)}},{key:"_isLinkOk",value:function(e){return null!==e&&"object"===(void 0===e?"undefined":r(e))&&(!this.prefetched.has(e.href)&&e.origin===this.config.siteUrl&&-1===e.href.indexOf("?")&&-1===e.href.indexOf("#")&&!this.regex.excludeUris.test(e.href)&&!this.regex.images.test(e.href))}}],[{key:"run",value:function(){"undefined"!=typeof RocketPreloadLinksConfig&&new n(new RocketBrowserCompatibilityChecker({capture:!0,passive:!0}),RocketPreloadLinksConfig).init()}}]),n}();t.run(); 4628}()); 4629/* ]]> */ 4630</script>
4630 4631 4632
4632<script src="https://www.bestpcbs.com/blog/wp-content/themes/default/2024/js/jquery-3.5.1.min.js" defer></script>
4632 4633
4633<script src="https://www.bestpcbs.com/blog/wp-content/themes/default/2024/js/swiper.min.js" defer></script>
4633 4634
4634<script src="https://www.bestpcbs.com/blog/wp-content/themes/default/2024/js/fn.js" defer></script>
4634 4635
4635<script src="https://www.bestpcbs.com/blog/wp-content/themes/default/2024/js/load.js" defer></script>
4635 4636
4636<script src="https://www.bestpcbs.com/blog/wp-content/themes/default/2024/js/faq.js" defer></script>
4636 4637
4637<script src="https://www.bestpcbs.com/blog/wp-content/themes/default/2024/js/jquery.animateNumber.min.js" defer></script>
4637 4638<!-- 1DNA AI Agent Chat Widget --> 4639<!-- No API key needed - add your domain to the allowed list in Agent settings -->
4640<script src="https://agent.1dna.au/embed.js" 4641 data-agent-id="da69295c-a1ae-4cee-9352-a02333a8024b" 4642></script>
4642 4643</body> 4644</html> 4645 4646 4647<!-- This website is like a Rocket, isn't it? Performance optimized by WP Rocket. Learn more: https://wp-rocket.me - Debug: cached@1790913211 -->
Line numbers count LF bytes from the start of the resource, as the search results do. Vendor segments are library code the classifier recognised; they are stored but not indexed. Bytes are shown as Latin1 characters, one per byte.