https://simten.dev/assets/examples-Qt4sxgQ-.js

1import{j as t}from"./main-5zZu2UcF.js";import{c as a,a as p,A as m,d,e as g,D as f,f as b,X as x,b as s,O as A}from"./useCircuitSimulator-Ocs-zDtT.js";import{C as c}from"./CircuitEmbed-BaKGR7p9.js";import"./CircuitCanvas-9Oc83aTy.js";import"./index-C6v6OnJi.js";let H={title:"Examples",description:"Interactive circuit examples from half adder to Fibonacci generator"},q={contents:[{heading:"half-adder",content:"Two bits → sum + carry. The simplest arithmetic circuit. Toggle the switches to see how AND computes carry and XOR computes sum."},{heading:"full-adder",content:"Three bits (a + b + carry in) → sum + carry out. Reuses HalfAdder as a composite, and the simulator expands it to primitives automatically."},{heading:"counter",content:"Increments on each clock cycle. A register feeds its output through an adder that adds 1, and the result loops back. Step the clock to watch it count."},{heading:"fibonacci-generator",content:"Two registers and one adder produce the Fibonacci sequence every clock tick. A DFlipFlop seed trick injects +1 on the first tick only."},{heading:"design-patterns",content:"**Combinational**: no state, no clock. Outputs computed directly from inputs. Examples: gates, adders, muxes, ALUs."},{heading:"design-patterns",content:"**Sequential**: has state and clock. State updates on rising clock edge, outputs reflect current state. Examples: counters, registers, shift registers."},{heading:"design-patterns",content:"**Hierarchical composition**: build complex circuits from simpler ones. FullAdder from HalfAdder, ALU from Adder+Mux, CPU from ALU+RegisterFile+Memory."},{heading:"design-patterns",content:"**Feedback loops**: connect a node's output back to its input through a register. The register breaks the combinational loop by introducing a one-cycle delay. This is how counters, state machines, and CPUs work."}],headings:[{id:"half-adder",content:"Half Adder"},{id:"full-adder",content:"Full Adder"},{id:"counter",content:"Counter"},{id:"fibonacci-generator",content:"Fibonacci Generator"},{id:"design-patterns",content:"Design Patterns"}]};const l=a("HalfAdder",{inputs:{a:s,b:s},outputs:{sum:s,carry:s},nodes:{xor1:x,and1:b},connect:({inputs:o,outputs:e,nodes:{xor1:n,and1:r}})=>[o.a.to(n.a,r.a),o.b.to(n.b,r.b),n.out.to(e.sum),r.out.to(e.carry)]}),F=a("FullAdder",{inputs:{a:s,b:s,cin:s},outputs:{sum:s,cout:s},nodes:{ha1:l,ha2:l,or1:A},connect:({inputs:o,outputs:e,nodes:{ha1:n,ha2:r,or1:i}})=>[o.a.to(n.a),o.b.to(n.b),n.sum.to(r.a),o.cin.to(r.b),r.sum.to(e.sum),n.carry.to(i.a),r.carry.to(i.b),i.out.to(e.cout)]}),y=a("Counter",{outputs:{count:g(8)},nodes:{reg:d(),adder:m(),one:p({value:1})},connect:({outputs:o,nodes:{reg:e,adder:n,one:r}})=>[e.q.to(n.a,o.count),r.out.to(n.b,e.we),n.sum.to(e.data)]}),j=a("Fibonacci",{outputs:{fib:g(8)},nodes:{reg_a:d(),reg_b:d(),adder:m(),one:p({value:1}),init:f()},connect:({outputs:o,nodes:{reg_a:e,reg_b:n,adder:r,one:i,init:u}})=>[i.out.to(u.d,e.we,n.we),u.q_bar.to(r.carry_in),e.q.to(r.a),n.q.to(r.b),n.q.to(e.data),r.sum.to(n.data),n.q.to(o.fib)]});let U=[{depth:2,url:"#half-adder",title:t.jsx(t.Fragment,{children:"Half Adder"})},{depth:2,url:"#full-adder",title:t.jsx(t.Fragment,{children:"Full Adder"})},{depth:2,url:"#counter",title:t.jsx(t.Fragment,{children:"Counter"})},{depth:2,url:"#fibonacci-generator",title:t.jsx(t.Fragment,{children:"Fibonacci Generator"})},{depth:2,url:"#design-patterns",title:t.jsx(t.Fragment,{children:"Design Patterns"})}];function h(o){const e={h2:"h2",p:"p",strong:"strong",...o.components};return t.jsxs(t.Fragment,{children:[t.jsx(e.h2,{id:"half-adder",children:"Half Adder"}),`
2`,t.jsx(e.p,{children:"Two bits → sum + carry. The simplest arithmetic circuit. Toggle the switches to see how AND computes carry and XOR computes sum."}),`
3`,`
4`,t.jsx(c,{circuit:l,showControls:!0,title:"Half Adder",description:"Toggle the switches to see sum and carry"}),`
5`,t.jsx(e.h2,{id:"full-adder",children:"Full Adder"}),`
6`,t.jsx(e.p,{children:"Three bits (a + b + carry in) → sum + carry out. Reuses HalfAdder as a composite, and the simulator expands it to primitives automatically."}),`
7`,`
8`,t.jsx(c,{circuit:F,showControls:!0,title:"Full Adder",description:"Toggle switches, and notice how carry-in affects the output"}),`
9`,t.jsx(e.h2,{id:"counter",children:"Counter"}),`
10`,t.jsx(e.p,{children:"Increments on each clock cycle. A register feeds its output through an adder that adds 1, and the result loops back. Step the clock to watch it count."}),`
11`,`
12`,t.jsx(c,{circuit:y,showControls:!0,title:"8-Bit Counter",description:"Step the clock to watch it count up (wraps at 0xFF)"}),`
13`,t.jsx(e.h2,{id:"fibonacci-generator",children:"Fibonacci Generator"}),`
14`,t.jsx(e.p,{children:"Two registers and one adder produce the Fibonacci sequence every clock tick. A DFlipFlop seed trick injects +1 on the first tick only."}),`
15`,`
16`,t.jsx(c,{circuit:j,showControls:!0,title:"Fibonacci Generator",description:"Step to see: 1, 1, 2, 3, 5, 8, 13, 21, 34, 55... (wraps at 8-bit)"}),`
17`,t.jsx(e.h2,{id:"design-patterns",children:"Design Patterns"}),`
18`,t.jsxs(e.p,{children:[t.jsx(e.strong,{children:"Combinational"}),": no state, no clock. Outputs computed directly from inputs. Examples: gates, adders, muxes, ALUs."]}),`
19`,t.jsxs(e.p,{children:[t.jsx(e.strong,{children:"Sequential"}),": has state and clock. State updates on rising clock edge, outputs reflect current state. Examples: counters, registers, shift registers."]}),`
20`,t.jsxs(e.p,{children:[t.jsx(e.strong,{children:"Hierarchical composition"}),": build complex circuits from simpler ones. FullAdder from HalfAdder, ALU from Adder+Mux, CPU from ALU+RegisterFile+Memory."]}),`
21`,t.jsxs(e.p,{children:[t.jsx(e.strong,{children:"Feedback loops"}),": connect a node's output back to its input through a register. The register breaks the combinational loop by introducing a one-cycle delay. This is how counters, state machines, and CPUs work."]})]})}function R(o={}){const{wrapper:e}=o.components||{};return e?t.jsx(e,{...o,children:t.jsx(h,{...o})}):h(o)}export{y as Counter,j as Fibonacci,F as FullAdder,l as HalfAdder,R as default,H as frontmatter,q as structuredData,U as toc};